- May 21, 2015
-
-
Yegor Yefremov authored
This device is an industrial PC based on AM335x SoC. [ balbi@ti.com : updated to fit current mainline ] Signed-off-by:
Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by:
Felipe Balbi <balbi@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Nishanth Menon authored
UART3 wakeup takes place with iodaisy chain. enable the wakeup pin. Reported-by:
Suman Anna <s-anna@ti.com> Signed-off-by:
Nishanth Menon <nm@ti.com> [tony@atomide.com: tabify uart pins properly while at it] Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Marek Belisko authored
Add voice audio card which is used for telephony on gta04 board. gtm601 codec is UMTS modem with pcm interface which get samples from microphone and provide data from other party side. Use simple audio card to describe audio card. Signed-off-by:
Marek Belisko <marek@goldelico.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Eliad Peller authored
uart1 is used for connecting to wilink8 bluetooth subsystem. add the needed muxes and definitions. Signed-off-by:
Eliad Peller <eliad@wizery.com> Signed-off-by:
Eyal Reizer <eyalr@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Eyal Reizer authored
enable mmc3 used for wlan and uart3 used for bluetooth configure the gpios used for wlan and bluetooth controls add fixed voltage regulator used for wlan power control Signed-off-by:
Eyal Reizer <eyalr@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Marek Belisko authored
Enable omap-hdq for battery fuel gauge access. Signed-off-by:
Marek Belisko <marek@goldelico.com> Signed-off-by:
H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Andrey Skvortsov authored
According to the technical reference manual for AM35xx system controller module (SCM) PADCONFS core registers are divided in two regions: 0x48002030..0x48002268 and 0x480025d8..0x480025fc. First region is the same for all omap3 SoC and is described in omap3.dtsi. The second region is the same as in omap34xx (see omap34xx.dtsi) and omap35xx. The patch adds missing description for the second region. This patch was tested on AM3517. Signed-off-by:
Andrey Skvortsov <andrej.skvortzov@gmail.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
Tony Lindgren authored
The LogicPD Torpedo DM3730 devkit consists of a base board and two processor boards. One of the processor boards has a WLAN and the other one does not. Let's set up basic dts file so we can move to device tree only based booting over next few merge windows. So far I've tested that UARTs, MMC1, USB OTG, smsc911x, and basic PM support works. Note that the wireless support in kernel for wl1283 seems to be broken, it tries to load wl127x-nvs.bin instead of wl128x-nvs.bin with firmware. Cc: Tim Nordell <tim.nordell@logicpd.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
-
- Apr 22, 2015
-
-
Mathieu Olivari authored
Add the watchdog related entries to the Krait Processor Sub-system (KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock description of SLEEP_CLK, which will do for now. Signed-off-by:
Josh Cartwright <joshc@codeaurora.org> Signed-off-by:
Mathieu Olivari <mathieu@codeaurora.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Acked-by:
Guenter Roeck <linux@roeck-us.net> Signed-off-by:
Wim Van Sebroeck <wim@iguana.be>
-
- Apr 14, 2015
-
-
Tsahee Zidenberg authored
This patch adds device-tree entry for the internal pci bus on Alpine. Alpine's on-chip devices appear as pci devices on this bus. Signed-off-by:
Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
-
Arnd Bergmann authored
This reverts commit e6f219b8 . to fix a build error: arch/arm/boot/dts/mt8135-pinfunc.h:18:40: fatal error: dt-bindings/pinctrl/mt65xx.h: No such file or directory Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
-
- Apr 08, 2015
-
-
Thomas Petazzoni authored
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the capability of changing the location of their internal registers (i.e the registers for most hardware blocks inside the SoC). When coming out of reset, the internal registers are mapped at 0xd0000000, but since years and years, the tradition has been to have the internal registers remapped at 0xf1000000 by the bootloader, and Linux has since then assumed that the internal registers for the SoC were located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never been aware that those registers are remappable (and there is no way to know where they are mapped at runtime, since the register to configure the address of the registers is itself within the internal registers). Then came the Armada 370 and Armada XP, in which some of the very early silicon steppings had an issue, which forced to use 0xd0000000: the SoC was no longer working properly when the internal registers were remapped at 0xf1000000. This issue is only affecting very early silicon steppings and production steppings are not affected: the issue has been fixed in between. Since what we (Free Electrons) used to do the initial submission of the Armada 370 and Armada XP platforms was evaluation boards with those very early steppings, we submitted Device Tree that assumed the internal registers were mapped at 0xd0000000. This is the case for Armada 370 DB, Armada XP DB and Armada XP GP. However, in practice, since Marvell has been shipping the evaluation boards with production steppings of the SoC, they are shipping those boards with bootloaders that remap the registers to 0xf1000000. We have already changed this internal register address to 0xf1000000 for the Armada XP DB in commit 82066bdb and for the Armada XP GP in commit 91ed3220 (both merged in v3.15). We only recently got our hand on an Armada 370 DB with a production stepping of the SoC, which uses a bootloader that remaps internal registers at 0xf1000000. Therefore, this commit aligns the Armada 370 DB to be like the Armada XP DB and Armada XP GP: assume that the internal registers are mapped at 0xf1000000. We would like to stress out the fact that the usage of 0xd0000000 as the internal register base address was a temporary workaround for early steppings deficiencies, and that the real long-term solution is the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the life of the Marvell platform support in the kernel, as is confirmed by the usage of 0xf1000000 in all previous Marvell platforms (Dove, Kirkwood, Orion). There are unfortunately a number of commercial devices that continue to use 0xd0000000 even though they use production steppings of the SoC, simply because the vendors of such devices have never bothered using a more recent bootloader version from Marvell. There is not much we can do about it, and we plan on keeping 0xd0000000 in the Device Tree of such devices. The main reason for remapping the internal registers at 0xf1000000 instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB part of the physical address space for RAM. With registers at 0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because it's covered by the I/O registers. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Andrew Lunn <andrew@lunn.ch> Acked-by:
Jason Cooper <jason@lakedameon.net> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com>
-
- Apr 04, 2015
-
-
Nicolas Ferre authored
After 57a38eff (net: phy: micrel: disable broadcast for KSZ8081/KSZ8091) the macb1 interface refuses to work properly because it tries to cling to address 0 which isn't able to communicate in broadcast with the mac anymore. The micrel phy on the board is actually configured to show up at address 1. Adding the phy node and its real address fixes the issue. Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Johan Hovold <johan@kernel.org> Cc: <stable@vger.kernel.org> #3.19 Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Add ARM common idle state device bindings for cpuidle support for APQ 8064. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Add ARM common idle states device bindings for cpuidle support for APQ 8084. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Add ARM common idle states device bindings for cpuidle support for APQ 8974/8074. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Lina Iyer authored
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by:
Lina Iyer <lina.iyer@linaro.org> Reviewed-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Kenneth Westfield authored
Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC. Signed-off-by:
Kenneth Westfield <kwestfie@codeaurora.org> Acked-by:
Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Ivan T. Ivanov authored
PMA8084 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using AQP8084 based chipset. Signed-off-by:
Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Ivan T. Ivanov authored
PM8841 and PM8941 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using 8x74 based chipset. Signed-off-by:
Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Ivan T. Ivanov authored
Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974. Signed-off-by:
Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Kumar Gala authored
Add the node for the LPASS clock controller found on a few qcom SoCs so that the clock driver can probe. Signed-off-by:
Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> [sboyd@codeaurora.org: Added apq8064 and msm8960 nodes] Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by:
Andy Gross <agross@codeaurora.org> Signed-off-by:
Kumar Gala <galak@codeaurora.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
Olof Johansson authored
Reported-by:
Brian Norris <computersforpeace@gmail.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
- Apr 03, 2015
-
-
Sebastian Reichel authored
This adds support for the N900's accelerometer to the Nokia N900 DTS file. Signed-off-by:
Sebastian Reichel <sre@kernel.org> Acked-by:
Tony Lindgren <tony@atomide.com> Reviewed-by:
Éric Piel <eric.piel@tremplin-utc.net> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
Kaixu Xia authored
The coresight-default-sink configuration option has been removed from the framework. As such remove it from DT and bindings. Signed-off-by:
Kaixu Xia <xiakaixu@huawei.com> Signed-off-by:
Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-
Peter Griffin authored
Now there are generic phy type constants declared in phy.h, migrate over to using them rather than defining our own. This change has been done as one atomic commit to be bisectable. Note: The values of the defines are the same, so there is no ABI breakage with this patch. Signed-off-by:
Peter Griffin <peter.griffin@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Lee Jones <lee.jones@linaro.org> Acked-by:
Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
-
- Apr 02, 2015
-
-
Olof Johansson authored
File uses dash in the filename, not underscore. Reported-by:
Russell King <linux@arm.linux.org.uk> Signed-off-by:
Olof Johansson <olof@lixom.net>
-
- Apr 01, 2015
-
-
Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
-
Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
-
Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Reported-by:
Tony Lindgren <tony@atomide.com>
-
Tero Kristo authored
This patch creates an l4_wkup interconnect for AM43xx, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM nodea as the clock provider. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
-
Tero Kristo authored
Pinmux node should be a reference to the base one, not a complete re-write of it. Having the node like this also prevents modifying the node layout in the base am4372.dtsi file, which is needed for control module changes. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
-
Tero Kristo authored
This patch creates an l4_wkup interconnect for AM33xx, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by:
Tero Kristo <t-kristo@ti.com>
-
Tero Kristo authored
This patch creates an l4_core interconnect for OMAP3, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM node as the clock provider. Signed-off-by:
Tero Kristo <t-kristo@ti.com> Reported-by:
Tony Lindgren <tony@atomide.com>
-