- Oct 12, 2015
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Vincent Donnefort authored
This patch adds DT support for the Seagate NAS 2 and 4-Bay. Here are some information allowing to identify these devices: Product name | Seagate NAS 2-Bay | Seagate NAS 4-Bay Code name (board/PCB) | Dart 2-Bay | Dart 4-Bay Model name (case sticker) | SRPD20 | SRPD40 Material desc (product spec) | STCTxxxxxxx | STCUxxxxxxx Chipset list (common): - SoC Marvell Armada 370 88F6707, CPU @1.2GHz - SDRAM memory: 512MB DDR3 600MHz (16-bits bandwidth) - NAND flash 256MB, 8-bits (Micron MT29F2G08AAB or Hinyx H27U2G8F2CTR-BC) - 2 SATA II ports (SoC) - 1 Ethernet Gigabit ports (PHY Marvell 88E1518) - 2 USB3 host ports (PCIe controller ASM1042) - GPIO fan (4 speeds) - External I2C RTC (MCP7940NT) - 3 push buttons (power, backup and reset) - 2 SATA LEDs (bi-color, blue and red) - 1 power LED (bi-color, blue and red) Only on 4-Bay models: - 2 extra SATA III ports (PCIe AHCI controller Marvell 88SE9170) - 1 extra Ethernet Gigabit ports (PHY Marvell 88E1518) - I2C GPIO expander (PCA9554A) - 2 extra SATA LEDs (bi-color, blue and red) Note that support for the white SATA LEDs associated with HDDs 0 and 1 is missing. A dedicated LED driver is needed. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Oct 09, 2015
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Boris Brezillon authored
Explicitly use the SoC specific compatible strings in kirkwood.dtsi and dove.dtsi, so that the crypto devices have access to the TDMA feature when attached to the new CESA driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
The new bindings split the crypto and sram node in two separate devices. Modify the existing crypto nodes to match the new representation. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Define the crypto SRAM ranges so that the resources referenced by the sa-sram node can be properly extracted from the DT. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Add crypto related nodes in armada-38x.dtsi. [gregory.clement@free-electrons.com: Fix typo for compatible string armada38x instead of armada375] Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Sep 29, 2015
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Boris Brezillon authored
Define the crypto SRAM ranges so that the resources referenced by the sa-sram node can be properly extracted from the DT. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Add crypto related nodes in armada-375.dtsi. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Define the crypto SRAM ranges so that the resources referenced by the sa-sram node can be properly extracted from the DT. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Arnaud Ebalard authored
Add crypto related nodes in armada-370.dtsi. Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Define the crypto SRAM ranges so that the resources referenced by the sa-sram node can be properly extracted from the DT. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Boris Brezillon authored
Add crypto related nodes to armada-xp.dtsi. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Thomas Petazzoni authored
This commit adds the description of the CPU config registers in the Armada 370 and Armada XP Device Tree. Since the registers are in fact different between the two SoCs, a different compatible string is used. Note that the Armada 370 node is currently unused, but it is nonetheless added for consistency with the addition on the Armada XP side. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Sep 11, 2015
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Yinghai Lu authored
When loading x86 64bit kernel above 4GiB with patched grub2, got kernel gunzip error. | early console in decompress_kernel | decompress_kernel: | input: [0x807f2143b4-0x807ff61aee] | output: [0x807cc00000-0x807f3ea29b] 0x027ea29c: output_len | boot via startup_64 | KASLR using RDTSC... | new output: [0x46fe000000-0x470138cfff] 0x0338d000: output_run_size | decompress: [0x46fe000000-0x47007ea29b] <=== [0x807f2143b4-0x807ff61aee] | | Decompressing Linux... gz... | | uncompression error | | -- System halted the new buffer is at 0x46fe000000ULL, decompressor_gzip is using 0xffffffb901ffffff as out_len. gunzip in lib/zlib_inflate/inflate.c cap that len to 0x01ffffff and decompress fails later. We could hit this problem with crashkernel booting that uses kexec loading kernel above 4GiB. We have decompress_* support: 1. inbuf[]/outbuf[] for kernel preboot. 2. inbuf[]/flush() for initramfs 3. fill()/flush() for initrd. This bug only affect kernel preboot path that use outbuf[]. Add __decompress and take real out_buf_len for gunzip instead of guessing wrong buf size. Fixes: 1431574a (lib/decompressors: fix "no limit" output buffer length) Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Jon Medhurst <tixy@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Sep 10, 2015
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Tim Bird <tim.bird@sonymobile.com> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mike Rapoport <mike.rapoport@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Add a label to the serial nodes that are being used for the console. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Sep 06, 2015
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Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SOC specific and the external clock is board dependent. Adding the corresponding nodes. Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Aug 28, 2015
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Vincent Donnefort authored
Since the LED modes mapping is no longer hardcoded inside the leds-ns2 driver, then it must be provided through the modes-map property in the ns2-leds nodes. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
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- Aug 25, 2015
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Linus Walleij authored
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Aug 22, 2015
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Tomeu Vizoso authored
Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is explicit. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Nicolas Chauvet authored
Current base address is wrong by 0x04 bytes for AHB bus device as shown in dmesg: tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address") checks for the low bit of the base address and removes theses 0x04 bytes at runtime. This patch fixes the original DTS, so upstream version doesn't need the workaround of the base address. As both addresses are valid, this patch doesn't break compatibility. Tested on tegra20-paz00 (aka ac100). Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Kyle Huey authored
This patch modifies the device tree for Tegra124 based devices to enable the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1 TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1. Signed-off-by: Kyle Huey <khuey@kylehuey.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Alexandre Courbot authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Alexandre Courbot authored
Nouveau can make use of the IOMMU to make physical appear linear in the GPU address space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Mikko Perttunen authored
Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Moritz Fischer authored
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 21, 2015
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Masahiro Yamada authored
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Brian Norris authored
When getting translated from a downstream device tree that used slightly different DT bindings, these regulators got labeled with the "on-in-suspend" state, when they were actually supposed to be turned off for S3 suspend. This was harmless, but not intentional, AFAICT. Let's turn them off to get the optimal power state. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
This DTS file was submitted with non-upstream bindings. I happened across this while reviewing the jaq DTS. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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