- May 23, 2017
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Shawn Lin authored
Make full use of 32 regions and increase IORESOURCE_MEM_64 so that we could have more chance to support PCIe switch with more endpoints attached to our RC. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Shawn Lin authored
In order to support multiple hierarchy of PCIe buses, for instance, PCIe switch, we need to extent bus-ranges to as max as possible. We have 32 regions and could support up to 31 buses except bus 0 for our root bridge. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add pinctrl for sdio, sdmmc, pcie, spdif, hdmi. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Kever Yang authored
Add qos setting reg for some peripheral like sd, usb, pcie. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- May 14, 2017
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Kever Yang authored
Firefly-rk3399 is a bord from T-Firefly, you can find detail about it here: http://en.t-firefly.com/en/firenow/Firefly_RK3399/ This patch add basic node for the board and make it able to bring up. Peripheral works: - usb hub which connect to ehci controller; - UART2 debug - eMMC - PCIe Not work: - USB 3.0 HOST, type-C port - sdio, sd-card Not test for other peripheral: - HDMI - Ethernet - OPTICAL - WiFi/BT - MIPI CSI/DSI - IR - EDP/DP Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 28, 2017
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Orson Zhai authored
SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum. According to regular hierarchy of sprd dts, whale2.dtsi contains SoC peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff and sp9860g dts is for the board level. Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Apr 25, 2017
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Konstantin Porotchkin authored
Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> [fixed up conflicts, added error handling --rmk] Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Viresh Kumar authored
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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- Apr 21, 2017
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Viresh Kumar authored
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Rob Herring <robh@kernel.org> [k.kozlowski: Split patch per ARM and ARM64] Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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Hoegeun Kwon authored
This patch adds the panel device tree node for s6e3hf2 display controller to TM2e dts. Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com> Reviewed-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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- Apr 19, 2017
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Sudeep Holla authored
Commit a8d4636f ("arm64: cacheinfo: Remove CCSIDR-based cache information probing") removed mechanism to extract cache information based on CCSIDR register as the architecture explicitly states no inference about the actual sizes of caches based on CCSIDR registers. Commit 9a802431 ("arm64: cacheinfo: add support to override cache levels via device tree") had already provided options to override cache information from the device tree. This patch adds the information about L1 and L2 caches on all variants of Juno platform. Cc: Will Deacon <will.deacon@arm.com> Cc: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Sudeep Holla authored
This patch fixes the following set of warnings on juno. smb@08000000 unit name should not have leading 0s sysctl@020000 simple-bus unit address format error, expected "20000" apbregs@010000 simple-bus unit address format error, expected "10000" mmci@050000 simple-bus unit address format error, expected "50000" kmi@060000 simple-bus unit address format error, expected "60000" kmi@070000 simple-bus unit address format error, expected "70000" wdt@0f0000 simple-bus unit address format error, expected "f0000" Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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- Apr 14, 2017
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Rob Herring authored
This adds the serial slave device for the WL1835 Bluetooth interface. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Wei Xu <xuwei5@hisilicon.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Marcel Holtmann <marcel@holtmann.org>
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- Apr 12, 2017
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Antoine Tenart authored
Enable the cryptographic engine available in the CP110 master on the Armada 8040 DB. Do not enable the one in the CP110 salve for now, as we do not support multiple cryptographic engines yet. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Enable the cryptographic engine available in the CP110 master on the Armada 7040 DB. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Antoine Tenart authored
Add the description of the crypto engine hardware block for the Marvell Armada 7k and Armada 8k processors; for both the CP110 slave and master. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Apr 11, 2017
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Gregory CLEMENT authored
Also enable it on the Armada 7040 DB and Armada 8040 DB boards. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Gregory CLEMENT authored
Add the eMMC support for Armada 37xx SoC and enable it in the Armada 3720 DB board. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Apr 10, 2017
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Wang Xiaoyin authored
Add pinctrl dtsi file for HiKey960 development board, enable 5 pinmux devices and 1 pinconf device, also include some nodes of configurations for pins. Signed-off-by: Wang Xiaoyin <hw.wangxiaoyin@hisilicon.com> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Wei Xu authored
Enable the NIC and SAS nodes for the hip07-d05 board to support related functions. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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- Apr 08, 2017
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Wei Xu authored
Add 3 SAS host controller nodes and the dependent subctrl node to enable the SAS and SATA function for the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Wei Xu authored
Add the infiniband node to support the RoCE function on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Wei Xu authored
Add MDIO, SerDes, Port and realted HNS nodes to support the network on the hip07 SoC. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Wei Xu authored
Add mbigen nodes for the hip07 SoC those will be used for the SAS, XGE and PCIe host controllers. Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Andy Yan authored
Commit 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") sets the memory size to 2 GB, but this board only has 1 GB DRAM, so change it to the correct value here. Fixes: 122682b2abb6 ("arm64: dts: rockchip: Add PX5 Evaluation board") Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 06, 2017
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Icenowy Zheng authored
The USB PHY in A64 has a "pmu0" region, which controls the EHCI/OHCI controller pair that can be connected to the PHY0. Add the MMIO region for PHY node. Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jiancheng Xue authored
Add basic dts files for hi3798cv200-poplar board. Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. The board features the Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Daniel Lezcano authored
The MMC hosts could be left in an unconsistent or uninitialized state from the firmware. Instead of assuming, the firmware did the right things, let's reset the host controllers. This change fixes a bug when the mmc2/sdio is initialized leading to a hung task: [ 242.704294] INFO: task kworker/7:1:675 blocked for more than 120 seconds. [ 242.711129] Not tainted 4.9.0-rc8-00017-gcf0251f #3 [ 242.716571] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 242.724435] kworker/7:1 D 0 675 2 0x00000000 [ 242.729973] Workqueue: events_freezable mmc_rescan [ 242.734796] Call trace: [ 242.737269] [<ffff00000808611c>] __switch_to+0xa8/0xb4 [ 242.742437] [<ffff000008d07c04>] __schedule+0x1c0/0x67c [ 242.747689] [<ffff000008d08254>] schedule+0x40/0xa0 [ 242.752594] [<ffff000008d0b284>] schedule_timeout+0x1c4/0x35c [ 242.758366] [<ffff000008d08e38>] wait_for_common+0xd0/0x15c [ 242.763964] [<ffff000008d09008>] wait_for_completion+0x28/0x34 [ 242.769825] [<ffff000008a1a9f4>] mmc_wait_for_req_done+0x40/0x124 [ 242.775949] [<ffff000008a1ab98>] mmc_wait_for_req+0xc0/0xf8 [ 242.781549] [<ffff000008a1ac3c>] mmc_wait_for_cmd+0x6c/0x84 [ 242.787149] [<ffff000008a26610>] mmc_io_rw_direct_host+0x9c/0x114 [ 242.793270] [<ffff000008a26aa0>] sdio_reset+0x34/0x7c [ 242.798347] [<ffff000008a1d46c>] mmc_rescan+0x2fc/0x360 [ ... ] Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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Geert Uytterhoeven authored
The current practice is to not add _clk suffixes to clock node names in DT, as these names are used as the actual clock names. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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- Apr 05, 2017
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Neil Armstrong authored
Add HDMI output and connector nodes. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Neil Armstrong authored
The HDMI modes needs more CMA memory to be reserved at boot-time. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Heiner Kallweit authored
Now that 3adbf342 "iio: adc: add a driver for the SAR ADC found in Amlogic Meson SoCs" has added support for the ADC, let's enable it on Odroid C2. Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Liang Chen authored
This patch add rk3328-evb.dts for RK3328 evaluation board. Tested on RK3328 evb. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Liang Chen authored
This patch adds core dtsi file for Rockchip RK3328 SoCs. Signed-off-by: Liang Chen <cl@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Apr 04, 2017
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Icenowy Zheng authored
Allwinner A64 have a dedicated pin controller to manage the PL pin bank. As the driver and the required clock support are added, add the device node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Icenowy Zheng authored
A64 SoC have a CCU (r_ccu) in PRCM block. Add the device node for it. The mux 3 of R_CCU is an internal oscillator, which is 16MHz according to the user manual, and has only 30% accuracy based on our experience on older SoCs. The real mesaured value of it on two Pine64 boards is around 11MHz, which is around 70% of 16MHz. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Jon Hunter authored
Update the Tegra132 flowctrl compatible string to include "nvidia,tegra132-flowctrl" so it is aligned with the flowctrl binding documentation. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Alexandre Courbot authored
Add the DT node for the GP10B GPU on Tegra186. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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- Mar 31, 2017
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Rob Herring authored
dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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Jayachandran C authored
Move and update device tree files as part of transition from Broadcom Vulcan to Cavium ThunderX2. The changes are to: * rename dts/broadcom/vulcan.dtsi to cavium/thunder2-99xx.dtsi, update cpu cores to be "cavium,thunder2", and update SoC to be "cavium,thunderx2-cn9900" * move SoC dts/broadcom/vulcan-eval.dtsi to cavium/thunder2-99xx.dtsi and update board name string * Update dts/broadcom/Makefile not to build vulcan dtbs * Update dts/cavium/Makefile to build thunder2 dtbs No changes to the dts contents except the updated "compatible" and "model" properties. Signed-off-by: Jayachandran C <jnair@caviumnetworks.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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