- Oct 03, 2013
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Thomas Petazzoni authored
The Armada XP Matrix board is the mother board of a more complex system. The mother board uses an Armada XP MV78460, 4 serial ports, 2 SATA ports, one Ethernet connection, a PCIe port and a USB port. All those devices are enabled in the Device Tree added by this patch. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Luka Perkov authored
Also, add some trivial whitespace cleanup. Signed-off-by: Luka Perkov <luka@openwrt.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Oct 02, 2013
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Jason Gunthorpe authored
There should be no nodes that are not children of the mbus. Move the nand node under the mbus, and rework the board .dts files to use an & reference to the nand node. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Jason Gunthorpe authored
There should be no nodes that are not children of the mbus. Move the crypto node under the mbus. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Jason Gunthorpe authored
kirkwood_setup_wins is the last manual caller of mbus in kirkwood, don't call it for DT boards and rely on the DT having a mbus node with a proper ranges property to setup these windows. Move all the mbus ranges properties for all boards into kirkwood.dtsi, since they are currently all the same. This makes the DT self consistent, since the physical address of the NAND and CRYPTO are both referenced internally. The arbitary Linux constants KIRKWOOD_NAND_MEM_PHYS_BASE and KIRKWOOD_SRAM_PHYS_BASE no longer have to match the DT values. Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Sep 30, 2013
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Sebastian Hesselbarth authored
This adds an initial DT file for the Globalscale D3Plug with Dove SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
With mbus node in place, now relocate all internal device nodes to internal-regs node with proper address ranges. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a MBus node including ranges and pcie apertures required later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a macro used for defining address window's target ID and attribute cells for the MBus ranges entry. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This coverts Dove DT board files to preprocessor includes instead of dtc includes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
Adds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Sep 18, 2013
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Gregory CLEMENT authored
The mv64xxx-i2c embedded in the Armada XP have a new feature to offload i2c transaction. This new version of the IP come also with some errata. This lead to the introduction to a another compatible string. This commit split the i2c information into armada-370.dtsi and armada-xp.dtsi. Most of the data remains the same and stay in the common file Armada-370-xp.dtsi. With this new feature the size of the registers are bigger for Armada XP and the new compatible string is used. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Sep 13, 2013
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Martin Schwidefsky authored
After the last architecture switched to generic hard irqs the config options HAVE_GENERIC_HARDIRQS & GENERIC_HARDIRQS and the related code for !CONFIG_GENERIC_HARDIRQS can be removed. Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
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Johannes Weiner authored
Unlike global OOM handling, memory cgroup code will invoke the OOM killer in any OOM situation because it has no way of telling faults occuring in kernel context - which could be handled more gracefully - from user-triggered faults. Pass a flag that identifies faults originating in user space from the architecture-specific fault handlers to generic code so that memcg OOM handling can be improved. Signed-off-by: Johannes Weiner <hannes@cmpxchg.org> Reviewed-by: Michal Hocko <mhocko@suse.cz> Cc: David Rientjes <rientjes@google.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: azurIt <azurit@pobox.sk> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Johannes Weiner authored
Kernel faults are expected to handle OOM conditions gracefully (gup, uaccess etc.), so they should never invoke the OOM killer. Reserve this for faults triggered in user context when it is the only option. Most architectures already do this, fix up the remaining few. Signed-off-by: Johannes Weiner <hannes@cmpxchg.org> Reviewed-by: Michal Hocko <mhocko@suse.cz> Acked-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: David Rientjes <rientjes@google.com> Cc: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: azurIt <azurit@pobox.sk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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Russell King authored
Keep arch/arm/Kconfig select statements sorted alphabetically. I've added a comment at the bottom of the main bank for CONFIG_ARM to this effect so hopefully this will keep things more in order. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Maxime Ripard authored
The A20-olinuxino-micro has the EMAC wired in. Enable it in the DT so that we can use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The Cubieboard2, just like its A10 counterpart, has the Ethernet wired in. Enable it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The A20 has several muxing options for the EMAC. Yet, the currently supported boards only use one set of them. Add that pin set to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The Allwinner A20 SoC also have the EMAC found on the A10 and A10s. Enable the support for it in the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Sep 12, 2013
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Naoya Horiguchi authored
Currently hugepage migration works well only for pmd-based hugepages (mainly due to lack of testing,) so we had better not enable migration of other levels of hugepages until we are ready for it. Some users of hugepage migration (mbind, move_pages, and migrate_pages) do page table walk and check pud/pmd_huge() there, so they are safe. But the other users (softoffline and memory hotremove) don't do this, so without this patch they can try to migrate unexpected types of hugepages. To prevent this, we introduce hugepage_migration_support() as an architecture dependent check of whether hugepage are implemented on a pmd basis or not. And on some architecture multiple sizes of hugepages are available, so hugepage_migration_support() also checks hugepage size. Signed-off-by: Naoya Horiguchi <n-horiguchi@ah.jp.nec.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Hillf Danton <dhillf@gmail.com> Cc: Wanpeng Li <liwanp@linux.vnet.ibm.com> Cc: Mel Gorman <mgorman@suse.de> Cc: Hugh Dickins <hughd@google.com> Cc: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Michal Hocko <mhocko@suse.cz> Cc: Rik van Riel <riel@redhat.com> Cc: "Aneesh Kumar K.V" <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Sep 11, 2013
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Russell King authored
Olof Johansson reports that the tests against HZ_FIXED seem non-functional. Fix this by using '0' as a sentinel for "not specified" and test against that instead. Reported-by: Olof Johansson <olof@lixom.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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- Sep 10, 2013
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Nicolas Pitre authored
This fixes the following build error: /tmp/cce439dZ.s: Assembler messages: /tmp/cce439dZ.s:506: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:512: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:513: Error: selected processor does not support ARM mode `dsb ' /tmp/cce439dZ.s:583: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:589: Error: selected processor does not support ARM mode `isb ' /tmp/cce439dZ.s:590: Error: selected processor does not support ARM mode `dsb ' Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Nicolas Pitre <nico@linaro.org> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Simon Horman authored
As of 8d3214c4 ("sh_eth: remove 'register_type' field from 'struct sh_eth_plat_data'") is is no longer necessary or correct to use the 'register_type' field from 'struct sh_eth_plat_data' and doing so results in a build error. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Commit a6e56c28 (ARM: pxa: ssp: add DT bindings) causes warnings when built: arch/arm/plat-pxa/ssp.c: In function 'pxa_ssp_probe': arch/arm/plat-pxa/ssp.c:145:17: warning: 'dma_spec.args[0]' may be used uninitialized in this function [-Wmaybe-uninitialized] Resolve by checking return values and aborting when lookups fail. Cc: Daniel Mack <zonque@gmail.com> Cc: Mark Brown <broonie@linaro.org> Cc: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Sep 09, 2013
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Ard Biesheuvel authored
Commit 01956597 introduced a NEON accelerated version of the xor_blocks() function, but it needs the changes in this patch to allow it to be built as a module rather than statically into the kernel. This patch creates a separate module xor-neon.ko which exports the NEON inner xor_blocks() functions depended upon by the regular xor.ko if it is built with CONFIG_KERNEL_MODE_NEON=y Reported-by: Josh Boyer <jwboyer@fedoraproject.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Julien Grall authored
When linux is running as dom0, Xen doesn't show the physical cpu but a virtual CPU. On some ARM SOC (for instance the exynos 5250), linux registers callbacks for cpuidle and cpufreq. When these callbacks are called, they will modify directly the physical cpu not the virtual one. It can impact the whole board instead of only dom0. Signed-off-by: Julien Grall <julien.grall@linaro.org> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Rob Herring authored
xen_pm_init was unconditionally setting pm_power_off and arm_pm_restart function pointers. This breaks multi-platform kernels. Make this conditional on running as a Xen guest and make it a late_initcall to ensure it is setup after platform code for Dom0. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com> CC: stable@vger.kernel.org
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- Sep 07, 2013
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Tomasz Figa authored
Since pwm-samsung bindings require at least one clock to be specified, this patch adds the missing clocks and clock-names properties to specify clocks used by PWM block on Exynos4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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- Sep 05, 2013
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Peter Maydell authored
The SMAP register offsets in the versatile PCI controller code were all off by four. (This didn't have any observable bad effects because on this board PHYS_OFFSET is zero, and (a) writing zero to the flags register at offset 0x10 has no effect and (b) the reset value of the SMAP register is zero anyway, so failing to write SMAP2 didn't matter.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Peter Maydell authored
The versatile PCI controller code was confused between the PCI I/O window (at 0x43000000) and the first PCI memory window (at 0x44000000). Pass the correct base address to pci_remap_io() so that PCI I/O accesses work. Since the first PCI memory window isn't used at all (it's an odd size), rename the associated variables and labels so that it's clear that it isn't related to the I/O window. This has been tested and confirmed to fix PCI I/O accesses both on physical PB926+PCI backplane hardware and on QEMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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Peter Maydell authored
The PCI controller code for the Versatile board has never had the correct IRQ mapping for hardware. For many years it had an odd mapping ("all interrupts are int 27") which aligned with the equivalent bug in QEMU. However as of commit 1bc39ac5 the mapping changed and no longer matched either hardware or QEMU, with the result that any PCI card beyond the first in QEMU would not have functioning interrupts; for example a boot with a SCSI controller would time out as follows: ------------ sym0: <895a> rev 0x0 at pci 0000:00:0d.0 irq 92 sym0: SCSI BUS has been reset. scsi0 : sym-2.2.3 [...] scsi 0:0:0:0: ABORT operation started scsi 0:0:0:0: ABORT operation timed-out. scsi 0:0:0:0: DEVICE RESET operation started scsi 0:0:0:0: DEVICE RESET operation timed-out. scsi 0:0:0:0: BUS RESET operation started scsi 0:0:0:0: BUS RESET operation timed-out. scsi 0:0:0:0: HOST RESET operation started sym0: SCSI BUS has been reset ------------ Fix the mapping so that it matches real hardware (checked against the schematics for PB926 and backplane, and tested against the hardware). This allows PCI cards using interrupts to work on hardware for the first time; this change will also work with QEMU 1.5 or later, where the equivalent bugs in the modelling of the hardware have been fixed. Although QEMU will attempt to autodetect whether the kernel is expecting the long-standing "everything is int 27" mapping or the one hardware has, for certainty we force it into "definitely behave like hardware mode"; this will avoid unexpected surprises later if we implement sparse irqs. This is harmless on hardware. Thanks to Paul Gortmaker for bisecting the problem and finding an initial solution, to Russell King for providing the correct interrupt mapping, and to Guenter Roeck for providing an initial version of this patch and prodding me into relocating the hardware and retesting everything. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Cc: stable@vger.kernel.org Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@linaro.org>
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- Sep 04, 2013
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Joel Fernandes authored
Manual trigger for events missed as a result of splitting a scatter gather list and DMA'ing it in batches. Add a helper function to trigger a channel incase any such events are missed. Signed-off-by: Joel Fernandes <joelf@ti.com> Acked-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
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- Sep 03, 2013
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Laurent Pinchart authored
Replace the numerical polarity flags with the PWM_POLARITY_INVERTED symbolic constant. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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Petr Štetiar authored
Second UART doesn't have modem interface, so any attempt to use set_mctrl() it produce unwanted garbage on the line. There's no such 0x100 register offset for the second UART either. Signed-off-by: Petr Štetiar <ynezz@true.cz> Cc: Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Ryan Mallon <rmallon@gmail.com>
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Ezequiel Garcia authored
This is almost cosmetic: we achieve a bit of consistency with other clocksource drivers by using the CLOCKSOURCE_OF_DECLARE macro for the boilerplate code. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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- Sep 02, 2013
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Dan Aloni authored
Signed-off-by: Dan Aloni <alonid@stratoscale.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Haojian Zhuang authored
Support UART0 debug ll on Hisilicon Hi3620 SoC & Hi3716 SoC. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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