- Sep 30, 2015
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Javier Martinez Canillas authored
There are 2 revisions of the Exynos5250 Snow Chromebook that were shipped: Rev4 and Rev5. The only difference between these 2 revisions is the codec, Rev4 has a max98095 codec while Rev5 has a max98090. Mainline only supports Rev4 so this patch moves the common device nodes to a DTSI file and adds a DTS for the Exynos5250 Snow Rev5. The Snow Rev5 DTS is based on the DTS found in the ChromiumOS 3.8 tree. Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com> Tested-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com> Reviewed-by: Douglas Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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- Sep 17, 2015
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Krzysztof Kozlowski authored
Add Hardkernel Odroid XU4 board Device Tree sources. The board differs from Odroid XU3 and XU3-Lite by: 1. No green and red LEDs (except standard red power LED). 2. Only two PWM outputs are used (fan and blue LED) 3. No audio codec. 4. Two USB3 ports in host mode (no micro USB3 connector for OTG). 5. Realtek RTL8153-CG gigabit network adapter (instead of SMSC9514). 6. Additional connector with IO ports (I2S_0, I2C_5). 7. No DisplayPort (like XU3-Lite). 8. No TI INA231 power measurement sensors (like XU3-Lite). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Krzysztof Kozlowski authored
The Odroid XU4 board does not have audio codec so before adding DTS for new board split the audio codec to separate DTSI file. Include the audio codec DTSI in Odroid XU3 and XU3-Lite boards. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Krzysztof Kozlowski authored
The Odroid XU3 family boards have ACOKB pin of PMIC grounded, instead of pulled up as usual. This means that PMIC must manually set PWRHOLD field in its CTRL1 register to low before initiating power down. This fixes Odroid XU3 powering off: [ 25.966053] reboot: Power down [ 25.967679] Power down. [ 26.070174] Power down failed, please power off system manually. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Reported-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Lukasz Majewski authored
With those bindings it is possible to use pwm-fan device available in Odroid U3 as a cooling device. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Eduardo Valentin <edubezval@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Kamil Debski authored
Add pwm-fan node to the Odroid-U3 board file to enable PWM control of the cooling fan. In addition, add the "pwm" label to the pwm@139D0000 node in the exynos4412.dtsi. Signed-off-by: Kamil Debski <k.debski@samsung.com> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Bartlomiej Zolnierkiewicz authored
Mark 800MHz OPP as a suspend opp for Exynos4412 based boards so effectively cpufreq-dt driver behavior w.r.t. suspend frequency matches what the old exynos-cpufreq driver has been doing. This patch fixes suspend/resume support on Exynos4412 based Trats2 board and reboot hang on Exynos4412 based Odroid U3 board. Cc: Thomas Abraham <thomas.ab@samsung.com> Cc: Javier Martinez Canillas <javier@osg.samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Cc: Tobias Jakobi <tjakobi@math.uni-bielefeld.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Krzysztof Kozlowski authored
The LEDs on Odroid XU3 family boards could not properly probe because PWM outputs were reduced only to PWM for fan. Fix it for Odroid XU3 and XU3-Lite boards by switching to usage of all 4 outputs (although the PWM for MIPI probably is redundant because board does not have MIPI connector available). This fixes warnings on dmesg: [ 4.838712] samsung-pwm 12dd0000.pwm: tried to request PWM channel 1 without output [ 4.838725] leds_pwm pwmleds: unable to request PWM for green:mmc0: -22 [ 4.838767] leds_pwm: probe of pwmleds failed with error -22 Fixes: b685d540 ("ARM: dts: Add pwm-fan node for exynos5422-odroidxu3") Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Kukjin Kim <kgene@kernel.org>
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- Sep 11, 2015
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Yinghai Lu authored
When loading x86 64bit kernel above 4GiB with patched grub2, got kernel gunzip error. | early console in decompress_kernel | decompress_kernel: | input: [0x807f2143b4-0x807ff61aee] | output: [0x807cc00000-0x807f3ea29b] 0x027ea29c: output_len | boot via startup_64 | KASLR using RDTSC... | new output: [0x46fe000000-0x470138cfff] 0x0338d000: output_run_size | decompress: [0x46fe000000-0x47007ea29b] <=== [0x807f2143b4-0x807ff61aee] | | Decompressing Linux... gz... | | uncompression error | | -- System halted the new buffer is at 0x46fe000000ULL, decompressor_gzip is using 0xffffffb901ffffff as out_len. gunzip in lib/zlib_inflate/inflate.c cap that len to 0x01ffffff and decompress fails later. We could hit this problem with crashkernel booting that uses kexec loading kernel above 4GiB. We have decompress_* support: 1. inbuf[]/outbuf[] for kernel preboot. 2. inbuf[]/flush() for initramfs 3. fill()/flush() for initrd. This bug only affect kernel preboot path that use outbuf[]. Add __decompress and take real out_buf_len for gunzip instead of guessing wrong buf size. Fixes: 1431574a (lib/decompressors: fix "no limit" output buffer length) Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Jon Medhurst <tixy@linaro.org> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: <stable@vger.kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Sep 10, 2015
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Tim Bird <tim.bird@sonymobile.com> Cc: Bjorn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mathieu Olivari <mathieu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Use stdout-path so that we don't have to put the console on the kernel command line. Cc: Mike Rapoport <mike.rapoport@gmail.com> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Stephen Boyd authored
Add a label to the serial nodes that are being used for the console. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Sep 06, 2015
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Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SOC specific and the external clock is board dependent. Adding the corresponding nodes. Signed-off-by: Keerthy <j-keerthy@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
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- Aug 28, 2015
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Vincent Donnefort authored
Since the LED modes mapping is no longer hardcoded inside the leds-ns2 driver, then it must be provided through the modes-map property in the ns2-leds nodes. Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jacek Anaszewski <j.anaszewski@samsung.com>
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- Aug 25, 2015
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Linus Walleij authored
The base addresses for the Ux500 PRCC controllers are hardcoded, let's move them to the clock node in the device tree and delete the constants. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Olof Johansson <olof@lixom.net> Acked-by: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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- Aug 22, 2015
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Tomeu Vizoso authored
Specify how the GPIOs map to the pins in Tegra SoCs, so the dependency is explicit. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Nicolas Chauvet authored
Current base address is wrong by 0x04 bytes for AHB bus device as shown in dmesg: tegra-ahb 6000c004.ahb: incorrect AHB base address in DT data - enabling workaround To correct old DTBs, commit ce7a10b0 ("ARM: 8334/1: amba: tegra-ahb: detect and correct bogus base address") checks for the low bit of the base address and removes theses 0x04 bytes at runtime. This patch fixes the original DTS, so upstream version doesn't need the workaround of the base address. As both addresses are valid, this patch doesn't break compatibility. Tested on tegra20-paz00 (aka ac100). Signed-off-by: Nicolas Chauvet <kwizart@gmail.com> Reviewed-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Kyle Huey authored
This patch modifies the device tree for Tegra124 based devices to enable the Cortex A15 PMU. The interrupt numbers are taken from NVIDIA Tegra K1 TRM (DP-06905-001_v03p). This patch was tested on a Jetson TK1. Signed-off-by: Kyle Huey <khuey@kylehuey.com> Acked-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Alexandre Courbot authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Add the device-tree node for the GK20A GPU and leave it disabled. It is the responsibility of the bootloader to enable it if the VPR registers have been programmed such that the GPU can operate. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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Alexandre Courbot authored
Nouveau can make use of the IOMMU to make physical appear linear in the GPU address space. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Mikko Perttunen authored
Specify the CPU voltage regulator for the cpufreq driver. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The Tegra124 cpufreq driver relies on certain clocks being present in the /cpus/cpu@0 node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tuomas Tynkkynen authored
The DFLL clocksource is a separate IP block from the usual clock-and-reset controller, so it gets its own device tree node. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Mikko Perttunen <mikko.perttunen@kapsi.fi> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
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Moritz Fischer authored
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 21, 2015
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Masahiro Yamada authored
This SoC is integrated with 4 Cortex-A9 cores. The GIC bindings document says that the bits[15:8] of the 3rd cell of the interrupts property represents PPI interrupt CPU mask. Because the timer interrupts are wired to all of the 4 cores, bits[15:8] should be set to 0xf. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Brian Norris authored
When getting translated from a downstream device tree that used slightly different DT bindings, these regulators got labeled with the "on-in-suspend" state, when they were actually supposed to be turned off for S3 suspend. This was harmless, but not intentional, AFAICT. Let's turn them off to get the optimal power state. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Brian Norris authored
This DTS file was submitted with non-upstream bindings. I happened across this while reviewing the jaq DTS. Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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- Aug 19, 2015
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Stephen Boyd authored
The sp810 clk driver is calling the clk consumer APIs from clk_prepare ops to change the parent to a 1 MHz fixed rate clock for each of the clocks that the driver provides. Use assigned-clock-parents for this instead of doing it in the driver to avoid using the consumer API in provider code. This also allows us to remove the usage of clk provider APIs that take a struct clk as an argument from the sp810 driver. Cc: Pawel Moll <pawel.moll@arm.com> Cc: Linus Walleij <linus.walleij@linaro.org> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 17, 2015
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Mauro Carvalho Chehab authored
There are some missing dependencies at the DT, as it looks for an I2C bus named "ssc2", but this is not defined. Probably, it misses some dependencies from some other tree. For now, revert this patch, to avoid build breakages. This reverts commit 5d8877b6 . Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
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- Aug 15, 2015
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Eduardo Valentin authored
This change is a code reorganization. Here we introduce serial_imx_enable_wakeup() helper function to do the job of configuring and preparing wakeup sources on imx serial device. The idea is to allow other parts of the code to call this function whenever the device is known to go to idle. Cc: Fabio Estevam <festevam@gmail.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jiri Slaby <jslaby@suse.com> Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Aug 14, 2015
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Mugunthan V N authored
CPSW driver has been updated with compatibles for enabling errata workarounds. So updating cpsw compatibles. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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