- Dec 05, 2014
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Olof Johansson authored
* clocksource/physical-timers: clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers clocksource: arch_timer: Fix code to use physical timers when requested
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Doug Anderson authored
Some 32-bit (ARMv7) systems are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset (CNTVOFF) between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) On systems like the above, it doesn't make sense to use the virtual counter. There's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. This adds an optional property which can inform the kernel of this situation, and firmware is free to remove the property if it is going to initialize the CNTVOFF registers when each CPU comes out of reset. Currently, the best course of action in this case is to use the physical timer, which is why it is important that CNTHCTL hasn't been changed from its reset value and it's a reasonable assumption given that the firmware has never entered HYP mode. Note that it's been said that on ARMv8 systems the firmware and kernel really can't be architected as described above. That means using the physical timer like this really only makes sense for ARMv7 systems. Signed-off-by:
Doug Anderson <dianders@chromium.org> Signed-off-by:
Sonny Rao <sonnyrao@chromium.org> Reviewed-by:
Mark Rutland <mark.rutland@arm.com> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by:
Catalin Marinas <catalin.marinas@arm.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Sonny Rao authored
This is a bug fix for using physical arch timers when the arch_timer_use_virtual boolean is false. It restores the arch_counter_get_cntpct() function after removal in 0d651e4e "clocksource: arch_timer: use virtual counters" We need this on certain ARMv7 systems which are architected like this: * The firmware doesn't know and doesn't care about hypervisor mode and we don't want to add the complexity of hypervisor there. * The firmware isn't involved in SMP bringup or resume. * The ARCH timer come up with an uninitialized offset between the virtual and physical counters. Each core gets a different random offset. * The device boots in "Secure SVC" mode. * Nothing has touched the reset value of CNTHCTL.PL1PCEN or CNTHCTL.PL1PCTEN (both default to 1 at reset) One example of such as system is RK3288 where it is much simpler to use the physical counter since there's nobody managing the offset and each time a core goes down and comes back up it will get reinitialized to some other random value. Fixes: 0d651e4e ("clocksource: arch_timer: use virtual counters") Cc: stable@vger.kernel.org Signed-off-by:
Sonny Rao <sonnyrao@chromium.org> Acked-by:
Catalin Marinas <catalin.marinas@arm.com> Acked-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Arnd Bergmann authored
Merge tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers Pull "ARM: tegra: IOMMU support for v3.19" from Thierry Reding: This adds the driver pieces required for IOMMU support on Tegra30, Tegra114 and Tegra124. * tag 'tegra-for-3.19-iommu' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: Add NVIDIA Tegra memory controller support of: Add NVIDIA Tegra memory controller binding ARM: tegra: Move AHB Kconfig to drivers/amba amba: Add Kconfig file clk: tegra: Implement memory-controller clock powerpc/iommu: Rename iommu_[un]map_sg functions iommu: Improve error handling when setting bus iommu iommu: Do more input validation in iommu_map_sg() iommu: Add iommu_map_sg() function Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Dec 04, 2014
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git://git.pengutronix.de/git/pza/linuxArnd Bergmann authored
Pull "Reset controller changes for v3.19" from Philipp Zabel: This adds a new driver for the sti soc family, and creates a reset_control_status interface, which is added to the existing drivers. * tag 'reset-for-3.19-2' of git://git.pengutronix.de/git/pza/linux: reset: add socfpga_reset_status reset: sti: Document sti-picophyreset controllers bindings. reset: stih407: Add softreset, powerdown and picophy controllers reset: stih407: Add reset controllers DT bindings reset: add reset_control_status helper function Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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https://github.com/brcm/linuxArnd Bergmann authored
This pull request contains the following changes to the Broadcom GISB bus arbiter from Kevin Cernekee: - Extend brcmstb GISB bus driver to work on MIPS (currently ARM-only) and support 65nm and 40nm MIPS-based chips such as: BCM7038, BCM7400 and BCM7435 * tag 'arm-soc/for-3.19/brcmstb-drivers' of https://github.com/brcm/linux: bus: brcmstb_gisb: Add register offset tables for older chips bus: brcmstb_gisb: Look up register offsets in a table bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses bus: brcmstb_gisb: Make the driver buildable on MIPS Conflicts: drivers/bus/brcmstb_gisb.c Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Thierry Reding authored
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by:
Joerg Roedel <jroedel@suse.de> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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- Nov 29, 2014
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Kevin Cernekee authored
This will select the appropriate register layout based on the DT "compatible" string. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Kevin Cernekee authored
There are at least 4 incompatible variations of this hardware block, so let's use the ARB_* constants as a table index instead of hardcoding specific register offsets. Also, allow for the possibility of adding old devices that are missing some of the registers. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Kevin Cernekee authored
These will be used to abstract out chip-to-chip differences. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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Kevin Cernekee authored
BCM7xxx ARM and MIPS platforms share a similar hardware block for reporting GISB errors, so they both benefit from the use of this driver. Conditionally compile the ARM-specific bus error handler so that the GISB error IRQ handler works on other architectures. Signed-off-by:
Kevin Cernekee <cernekee@gmail.com> Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com>
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- Nov 28, 2014
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Arnd Bergmann authored
Merge tag 'samsung-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/drivers Pull "Samsung driver update for v3.19" from Kukjin Kim: - Change samsung serial dependencies for exynos7 (ARMv8) * tag 'samsung-driver' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: serial: samsung: Fix serial config dependencies for exynos7 Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Nov 26, 2014
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Thierry Reding authored
The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. In addition, the memory controller implements an SMMU (IOMMU) which can translate I/O virtual addresses to physical addresses for clients. This is useful for scatter-gather operation on devices that don't support it natively and for virtualization or process separation. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
This will allow the Kconfig option to be shared among 32-bit and 64-bit ARM. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
Rather than duplicate the ARM_AMBA Kconfig symbol in both 32-bit and 64-bit ARM architectures, move the common definition to drivers/amba where dependent drivers will be located. Signed-off-by:
Thierry Reding <treding@nvidia.com>
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Thierry Reding authored
The memory controller clock runs either at half or the same frequency as the EMC clock. Reviewed-By:
Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by:
Mike Turquette <mturquette@linaro.org> Signed-off-by:
Thierry Reding <treding@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommuThierry Reding authored
This branch contains a couple of changes that will conflict with the Tegra SMMU driver rewrite. Since the driver is largely rewritten the conflict resolution is non-trivial.
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- Nov 21, 2014
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Pankaj Dubey authored
Exynos7 has a similar serial controller to that present in older Samsung SoCs. To re-use the existing serial driver on Exynos7 we need to have SERIAL_SAMSUNG_UARTS_4 and SERIAL_SAMSUNG_UARTS selected. This is not possible because these symbols are dependent on PLAT_SAMSUNG which is not present for the ARMv8 based exynos7. Change the dependency of these symbols from PLAT_SAMSUNG to the serial driver thus making it available on exynos7. As the existing platform specific code making use of these symbols is related to uart driver this change in dependency should not cause any issues. Signed-off-by:
Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by:
Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by:
Abhilash Kesavan <a.kesavan@samsung.com> Acked-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Florian Fainelli authored
Commit f1bee783 moved the call to hook_fault_code in brcmstb_gisb_arb_probe() which now calls a function annotated with __init, so this one must also be annotated with __init. In order to avoid introducing another section mismatch, call platform_driver_probe() manually and remove the .probe assignment from brcmstb_gisb_arb_driver, this is very similar to what drivers/pci/host/pci-imx6.c does since we basically have the same constraints here. Fixes: f1bee783 ("bus: brcmstb_gisb: register the fault code hook") Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
The recently introduced resume hook in the edma driver is not referenced when CONFIG_PM_SLEEP is not set, which results in a compile warning in keystone builds. This adds an appropriate #ifdef. Cc: Nishanth Menon <nm@ti.com> Cc: Daniel Mack <zonque@gmail.com> Cc: Joel Fernandes <joelf@ti.com> Acked-by:
Sekhar Nori <nsekhar@ti.com> Fixes: a2b11751 : ("ARM: common: edma: add suspend resume hook") Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'davinci-for-v3.19/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/drivers Pull "Adds suspend/resume support to EDMA driver" from Sekhar Nori: * tag 'davinci-for-v3.19/edma' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: common: edma: add suspend resume hook Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Nov 20, 2014
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Arnd Bergmann authored
This resolves some of the obvious conflicts between the at91 cleanup and drivers branches. Conflicts: arch/arm/mach-at91/at91sam9g45.c arch/arm/mach-at91/at91sam9rl.c drivers/rtc/Kconfig Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into next/drivers Pull "ARM: perf: updates for 3.19" from Will Deacon: This patch series takes us slightly further on the road to big.LITTLE support in perf. The main change enabling this is moving the CCI PMU driver away from the arm-pmu abstraction, allowing the arch code to focus specifically on support for CPU PMUs. * tag 'arm-perf-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux: arm: perf: fold hotplug notifier into arm_pmu arm: perf: dynamically allocate cpu hardware data arm: perf: fold percpu_pmu into pmu_hw_events arm: perf: kill get_hw_events() arm: perf: limit size of accounting data arm: perf: use IDR types for CPU PMUs arm: perf: make PMU probing data-driven arm: perf: add missing pr_info newlines arm: perf: factor out callchain code ARM: perf: use pr_* instead of printk ARM: perf: remove useless return and check of idx in counter handling bus: cci: move away from arm_pmu framework Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/drivers Pull "First batch of drivers for 3.19" from Nicolas Ferre: It is only about a not so recent driver for old platforms: RTT as RTC driver: - RTT as RTC driver enhancements and machine specific include files removal - RTT as RTC driver conversion to device tree * tag 'at91-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: rtc: at91sam9: add DT bindings documentation rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK ARM: at91: add clk_lookup entry for RTT devices rtc: at91sam9: rework the Kconfig description rtc: at91sam9: make use of syscon/regmap to access GPBR registers rtc: at91sam9: add DT support rtc: at91sam9: replace devm_ioremap by devm_ioremap_resource rtc: at91sam9: use standard readl/writel functions instead of raw versions rtc: at91sam9: remove references to mach specific headers Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'keystone-driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/drivers Pull "Keystone SOC Navigator driver non critical fixes frm Alex for 3.19" from Santosh Shilimkar: - Use list_for_each_entry_safe to prevent use after free - Return proper error if devm_kzalloc fails - Use list_first_entry_or_null() at appropriate places * tag 'keystone-driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: soc: ti: knav_qmss_queue: Use list_for_each_entry_safe to prevent use after free soc: ti: knav_qmss_queue: Return proper error if devm_kzalloc fails soc: ti: knav_qmss_queue: Fix unbalanced locking ins knav_pool_create() soc: ti: Use list_first_entry_or_null() at appropriate places Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
Merge tag 'omap-for-v3.19/w1-and-l3-noc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Pull "omap driver changes for v3.19" from Tony Lindgren: Few omap driver changes to add minimal device tree support for the omap 1w driver, and to fix resume and interrupt issues on the l3-noc driver. * tag 'omap-for-v3.19/w1-and-l3-noc' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: bus: omap_l3_noc: Correct returning IRQ_HANDLED unconditionally in the irq handler bus: omap_l3_noc: Add resume hook to restore context w1: omap-hdq: support device probing with device-tree Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Nov 18, 2014
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Daniel Mack authored
This patch makes the edma driver resume correctly after suspend. Tested on an AM33xx platform with cyclic audio streams and omap_hsmmc. All information can be reconstructed by already known runtime information. As we now use some functions that were previously only used from __init context, annotations had to be dropped. [nm@ti.com: added error handling for runtime + suspend_late/early_resume] Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Daniel Mack <zonque@gmail.com> Tested-by:
Joel Fernandes <joelf@ti.com> Acked-by:
Joel Fernandes <joelf@ti.com> [nsekhar@ti.com: remove unneeded pm_runtime_get_sync() from resume] Signed-off-by:
Sekhar Nori <nsekhar@ti.com>
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Joerg Roedel authored
The IOMMU-API gained support for a new iommu_map_sg function. This causes compile failures on powerpc because the function name is already globally used there. This patch renames adds a ppc_ prefix to these functions to solve the compile problem. Signed-off-by:
Joerg Roedel <jroedel@suse.de>
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- Nov 13, 2014
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Boris BREZILLON authored
Add RTT bindings documentation. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
The RTT block is using the slow clock which is accessible through the clk API. Use the clk API to retrieve, enable and get the slow clk rate instead of the AT91_SLOW_CLOCK macro (which hardcodes the slow clk rate). Doing this allows us to reference the clk thus preventing the CCF from disabling it during the "disable unused" phase. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
First export the clk32k clk. Then add clk_lookup entries for RTT devices so that rtc-at91sam9 driver can retrieve and manipulate the slow clk. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
Remove all references to AT91CAP9 SoC which has been removed. Rework help message to remove any specific references to AT91SAM9 SoCs. State that RTC_DRV_AT91SAM9_RTT and RTC_DRV_AT91SAM9_GPBR options are only used when booting non DT boards. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
The GPBR registers are not part of the RTT block and thus should not be defined in the reg property of the rtt node. Use syscon to provide a proper DT representation and reference the GPBR syscon device in a new "atmel,rtt-rtc-time-reg" property which store both the syscon device phandle and the register offset within the GPBR block. When using non DT boards, we won't be able to retrieve the syscon regmap, hence we need to create our own regmap using the memory region defined in the 2nd memory resource assigned to the RTT platform device. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
Add of_match_table to the existing driver so that rtt nodes defined in at91 DTs can be attached to this driver. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
Replace devm_ioremap calls by devm_ioremap_resource which already check resource consistency (resource != NULL) and print an error in case of failure. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
Raw versions of writel and writel should not be directly used and should be replaced by their relaxed versions (readl/writel_relaxed), which take endianness conversion into account. In this driver we prefer the standard readl/writel function which add the appropriate memory barrier around the access (the performance penalty is negligible for this kind of application). Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Boris BREZILLON authored
In order to support multi platform kernel drivers should not include machine specific headers. Copy RTT macros in the driver code and remove any machine specific headers. Signed-off-by:
Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by:
Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by:
Johan Hovold <johan@kernel.org> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Nov 12, 2014
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Keerthy authored
Correct returning IRQ_HANDLED unconditionally in the irq handler. Return IRQ_NONE for some interrupt which we do not expect to be handled in this handler. This prevents kernel stalling with back to back spurious interrupts. Fixes: 2722e56d ("OMAP4: l3: Introduce l3-interconnect error handling driver") Acked-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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Keerthy authored
On certain SoCs such as AM437x SoC, L3_noc error registers are maintained in power domain such as per domain which looses context as part of low power state such as RTC+DDR mode. On these platforms when we mask interrupts which we cannot handle, the source of these interrupts still remain on resume, however, the flag mux registers now contain their reset value (unmasked) - this breaks the system with infinite interrupts since we do not these interrupts to take place ever again. To handle this: restore the masking of interrupts which we have already recorded in the system as ones we cannot handle. Fixes: 2100b595 ("bus: omap_l3_noc: ignore masked out unclearable targets") Acked-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Keerthy <j-keerthy@ti.com> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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- Nov 11, 2014
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NeilBrown authored
This driver has no 'compatible' string and so is not found when using device-tree. Add one with value to match hdqw1w: 1w@480b2000 { device in omap3.dtsi. Signed-off-by:
NeilBrown <neilb@suse.de> Acked-by:
Evgeniy Polyakov <zbr@ioremap.net> Signed-off-by:
Tony Lindgren <tony@atomide.com>
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