- Jul 17, 2013
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Guennadi Liakhovetski authored
This patch adds a sample DT-based APE6EVM "reference" implementation. The use of platform-specific C-code should be avoided with this configuration as much as possible. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Magnus Damm authored
Add support for the SMSC ethernet controller found on the KZM9D board to the KZM9D DT Reference code. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Magnus Damm authored
Add a DT reference implementation for the KZM9D board. Only DT devices are used in this case. UART, STI, GPIO and SMP / GIC are all provided by emev2.dtsi. There is still a board specific C file used for enabling legacy SH clocks. This file will be removed after we have moved over to common clocks. Signed-off-by: Magnus Damm <damm@opensource.se> [horms+renesas@verge.net.au: Do not include trailing blank line in board-kzm9d-reference.c ] Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski authored
This adds DT templates for all MMCIF and SDHI controllers on r8a7790. They are added with status="disabled". To use them platform-specific DTs have to enable the required ones. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski authored
This adds DT templates for all MMCIF and SDHI controllers on r8a73a4. They are added with status="disabled". To use them platform-specific DTs have to enable the required ones. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Magnus Damm authored
Add GIO0->GIO4 device nodes to the EMEV2 dtsi file. Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Magnus Damm authored
Update the KZM9D DTS command line to remove following cruft: - console=tty0 - no graphic support upstream anyway - earlyprintk= - not supported by the 8250-em driver anyway - mem= - this is provided via DT anyway Signed-off-by: Magnus Damm <damm@opensource.se> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski authored
This patch adds OPPs to the CA15 DT node and a max8973 DT node to support clock and voltage scaling, using the cpufreq-cpu0 CPUFreq driver. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski authored
Add Device Tree nodes for the 9 I2C controllers on r8a73a4, compatible with the i2c-sh_mobile.c driver. Signed-off-by: Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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- Jul 10, 2013
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Kyungsik Lee authored
Integrates the LZ4 decompression code to the arm pre-boot code. Signed-off-by: Kyungsik Lee <kyungsik.lee@lge.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <rmk@arm.linux.org.uk> Cc: Borislav Petkov <bp@alien8.de> Cc: Florian Fainelli <florian@openwrt.org> Cc: Yann Collet <yann.collet.73@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Jul 04, 2013
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Xianglong Du authored
On CSR SiRFprimaII/atlasVI, there is a programmable 16-bit divider (RTC_DIV) that divides the input 32.768KHz clock to the frequency that users need (E.g. 1 Hz). The divided real-time clock will be used to drive a 32-bit counter (RTC_COUNTER) that provides users with the actual time. In each cycle of the divided real-time clock, there is a Hertz interrupt generated to the RISC. Users can also configure an alarm (RTC_ALARM). When RTC_COUNTER matches the alarm, there will be an alarm interrupt generated to the RISC. The system RTC can generate an alarm wake-up signal to notify the power controller to wake up from power saving mode. Signed-off-by: Xianglong Du <Xianglong.Du@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Cc: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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- Jul 03, 2013
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Stephen Warren authored
Commit 4c94c8b5 "ARM: tegra: update device trees for USB binding rework" added regulator definitions for GPIO-controlled USB VBUS. However, none of these contained the essential DT property enable-active-high. Add this so that the regulator definitions are correct. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Jun 28, 2013
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Rahul Sharma authored
This patch renames the combatible strings for hdmi, mixer, ddc and hdmiphy. It follows the convention of using compatible string which represent the SoC in which the IP was added for the first time. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com>
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Geert Uytterhoeven authored
Several drivers need font support independent of CONFIG_VT, cfr. commit 9cbce8d7e1dae0744ca4f68d62aa7de18196b6f4, "console/font: Refactor font support code selection logic"). Hence move the fonts and their support logic from drivers/video/console/ to its own library directory lib/fonts/. This also allows to limit processing of drivers/video/console/Makefile to CONFIG_VT=y again. [Kevin Hilman <khilman@linaro.org>: Update arch/arm/boot/compressed/Makefile] Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
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- Jun 27, 2013
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Fabio Estevam authored
Instead of using a GPIO to turn on/off the CAN transceiver, it is better to use a regulator as some systems may use a PMIC to power the CAN transceiver. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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Linus Walleij authored
This alters the local side address of the iospace to zero, non prefetchable memory local side address to 0x00000000 and prefetchable memory local side address to 0x10000000, so as to match the values actually poked in by the driver. Reported-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Manjunathappa, Prakash authored
function-mask DT property is now a mask for a pin at each pin offset inside a given pincontrol register. Fix DA850 DT data to reflect this change. Signed-off-by: Manjunathappa, Prakash <prakash.pm@ti.com> [nsekhar@ti.com: reword commit message for clarity] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Jingoo Han authored
This patch adds pcie controller node for exynos5440-ssdk5440, and also adds a phandle for pin controller node. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Jingoo Han authored
Exynos5440 has two PCIe controllers which can be used as root complex for PCIe interface. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Jun 26, 2013
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Jean-Christophe PLAGNIOL-VILLARD authored
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Nicolas Ferre authored
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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Nicolas Ferre authored
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
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Nicolas Ferre authored
In previous version of SPI driver we where using different compatibility stings for finding SPI features. We are now using the IP revision information. So we stay with the unique compatibility string for this driver: "atmel,at91rm9200-spi". Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Tested-by: Wenyou Yang <wenyou.yang@atmel.com>
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Srinivas Kandagatla authored
B2020 ADI board is reference board for STIH415/416 SOCs, it has 2 x UART, 4x USB, 1 x Ethernet, 1 x SATA, 1 x PCIe, and 2GB RAM with standard set-top box IPs. This patch adds initial support to B2020 with STiH415/416 with SBC_UART1 as console and a heard beat LED. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Srinivas Kandagatla authored
B2000 board is reference board for STIH415/416 SOCs, it has 2 x UART, 4x USB, 2 x Ethernet, 1 x SATA, 1 x PCIe, and 1GB RAM. This patch add initial support to b2000 with STiH415/416 with UART2 as console and a heard beat LED. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Olof Johansson <olof@lixom.net>
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Srinivas Kandagatla authored
The STiH416 is advanced HD AVC processor with 3D graphics acceleration and 1.2-GHz ARM Cortex-A9 SMP CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Srinivas Kandagatla authored
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Jun 24, 2013
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Marc Zyngier authored
arm26 support in Linux is long gone, yet it left an interresting, fossilized trace in the decompressor. Remove it so people won't get confused about what teqp is actually doing here... Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Ezequiel Garcia authored
The length of the registers area for the Marvell 370/XP Ethernet controller was incorrect in the .dtsi: 0x2500, while it should have been 0x4000. This problem wasn't noticed because there used to be a static mapping for all the MMIO register region set up by ->map_io(). The register length was fixed in all the other device tree files, except from the armada-xp-mv78260.dtsi, in the following commit: commit cf8088c5 Author: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Date: Tue May 21 12:33:27 2013 +0200 arm: mvebu: fix length of Ethernet registers area in .dtsi This commit fixes a kernel panic in mvneta_probe(), when the kernel tries to access the unmapped registers: [ 163.639092] mvneta d0070000.ethernet eth0: mac: 6e:3c:4f:87:17:2e [ 163.646962] mvneta d0074000.ethernet eth1: mac: 6a:04:4e:6f:f5:ef [ 163.654853] mvneta d0030000.ethernet eth2: mac: 2a:99:19:19:fc:4c [ 163.661258] Unable to handle kernel paging request at virtual address f011bcf0 [ 163.668523] pgd = c0004000 [ 163.671237] [f011bcf0] *pgd=2f006811, *pte=00000000, *ppte=00000000 [ 163.677565] Internal error: Oops: 807 [#1] SMP ARM [ 163.682370] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.10.0-rc6-01850-gba0682e #11 [ 163.690046] task: ef04c000 ti: ef03e000 task.ti: ef03e000 [ 163.695467] PC is at mvneta_probe+0x34c/0xabc [...] Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Jun 22, 2013
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Daniel Tang authored
This patch adds device trees for describing the TI-Nspire hardware. Changes between v1 and v2: * Change "keymap" binding to the standard "linux,keymap" binding. Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Jun 21, 2013
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Ezequiel Garcia authored
Although the internal register window size is 1 MiB, the previous ranges translation for the internal register space had a size of 0x4000000. This was done to allow the crypto and nand node to access the corresponding 'sram' and 'nand' decoding windows. In order to describe the hardware more accurately, we declare the real 1 MiB internal register space in the ranges, and add a translation entry for the nand node to access the 'nand' window. This commit will make future improvements on the MBus DT binding easier. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Lee Jones authored
When this node was added, the AB8500 GPIO driver was pretty broken. As a hack, we pretended that NOMADIK GPIO 26 was the correct on/off pin, as it was unused. It worked because AB8500 GPIO 26 was in an 'always on from boot' state. Now the AB8500 GPIO driver is working, the default state for all the pins is 'off'. Let's flip back over to use the correct GPIO which is _actually_ attached to the regulator. We're also taking the opportunity to straighten out some formatting misdemeanours, swapping spaces for tabs. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Lee Jones authored
Here we're adding a node for the AB8500 GPIO device. This will allow other DT:ed components to obtain GPIOs for use within their drivers. Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org>
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Heiko Stuebner authored
This adds a generic devicetree board file and a dtsi for boards based on the RK3066a SoCs from Rockchip. Apart from the generic parts (gic, clocks, pinctrl) the only components currently supported are the timers, uarts and mmc ports (all DesignWare- based). Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Olof Johansson <olof@lixom.net>
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Heiko Stuebner authored
This adds a basic clock setup for rk3066a SoCs. Only the gates are set up currently, as the mux and dividers should use the upcoming generic devicetree bindings. Clocks whose rates need to be known are supplied by fixed-rate "dummy"-clocks that provide the correct rate. This is uncritical insofar that the only bootloader currently in existence for Rockchip devices is the propietary Rockchip one that always setups the clocks in the necessary way. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Mike Turquette <mturquette@linaro.org>
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Matt Porter authored
CodingStyle does not allow C99 style comments. Since the dts files live in the kernel for now, make this compliant. Signed-off-by: Matt Porter <matt.porter@linaro.org> Acked-by: Christian Daudt <csd@broadcom.com>
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Christian Daudt authored
Add SDHCI bindings for the Broadcom 281xx SoCs. Changes from V2: - Documentation cleanups Changes from V1: - split original patch into 2, one for driver and this one for dt Signed-off-by: Christian Daudt <csd@broadcom.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
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- Jun 20, 2013
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Philip Avinash authored
Replace /include/ by #include for da850 device tree files, in order to use the C pre-processor, making use of #define features possible. Signed-off-by: Philip Avinash <avinashphilip@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
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Linus Walleij authored
This revamps the device tree to fit with the new clock implementation and brings it quite a bit closer to how the hardware actually works. After this the clock implementation knows about all clock gates and will gate off all unused clocks at boot time and save a bit of power. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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