- Nov 24, 2016
-
-
Schuyler Patton authored
The AM571x-IDK board is a board based on TI's AM5718 SOC which has a single core 1.5GHz A15 processor. This board is a development platform for the Industrial market with: - 1GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - PRU-ICSS - uSD - 16GB eMMC - CAN - RS-485 - PCIe - USB3.0 - Video Input Port - Industrial IO port and expansion connector The link to the data sheet and TRM can be found here: http://www.ti.com/product/AM5718 Initial support is only for basic peripherals. Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Yegor Yefremov authored
phy-phandle is now a preferred method to reference a PHY device. Especially in regards to cpsw it enables PHY specific settings like max-speed etc. being specified in DTS. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Keerthy authored
The PMICs have POWERHOLD set by default which prevents PMIC shutdown even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority. So to enable pmic power off this property lets one over ride the default value and enable pmic power off. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Keerthy authored
The PMICs have POWERHOLD set by default which prevents PMIC shutdown even on DEV_CTRL On bit set to 0 as the Powerhold has higher priority. So to enable pmic power off this property lets one over ride the default value and enable pmic power off. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
- Nov 18, 2016
-
-
Andrew F. Davis authored
The TPIC2810 is available on both the AM571x and the AM572x IDKs and is attached to I2C1. Output is attached to the I/O header and 10 LEDs. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
The SN65HVS882 is available on both the AM572x and AM571x IDKs and is attached to SPI1. Input is attached to the I/O header. The load trigger is attached to GPIO3_19 on the AM572x IDK. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
The TPIC2810 is available on the AM437x IDK and is attached to I2C1. Output is attached to the I/O header and 10 LEDs. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
The SN65HVS882 is available on the AM437x IDK and is attached to SPI1. Input is attached to the I/O header. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
7 of the 8 ADC inputs on the am335x are connected to the Industrial I/O header, add this here. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
The LEDs tied to the Industrial I/O output pins are meant for providing status feed-back and are not the primary use for the pins. Disable this use by default. Also unify the LED naming across IDK platforms. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Andrew F. Davis authored
The SN65HVS882 is available on the AM335x-ICEv2 and is attached to SPI0. Input is attached to the I/O header. Signed-off-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Jyri Sarha authored
Add blue-and-red-wiring -property to LCDC node. Also adds comments on how to get support 24 bit RGB mode. After this patch am335x-boneblack support RGB565, BGR888, and XBGR8888 color formats. See details in Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt. The BBB has straight color wiring from am335x to tda19988, however the tda19988 can be configured to cross the blue and red wires. The comments show how to do that with video-ports property of tda19988 node and how to tell LCDC that blue and red wires are crossed, with blue-and-red-wiring LCDC node property. This changes supported color formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
- Nov 17, 2016
-
-
Sudeep Holla authored
Though the keyboard driver for GPIO buttons(gpio-keys) will continue to check for/support the legacy "gpio-key,wakeup" boolean property to enable gpio buttons as wakeup source, "wakeup-source" is the new standard binding. This patch replaces the legacy "gpio-key,wakeup" with the unified "wakeup-source" property in order to avoid any further copy-paste duplication. Cc: "Benoît Cousson" <bcousson@baylibre.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
- Nov 16, 2016
-
-
Tony Lindgren authored
Let's add minimal support for droid 4 with MMC and WLAN working. It can be booted with appended dtb using kexec to a state where MMC and WLAN work with currently no support for it's PMIC or display. Note that we are currently using fixed regulators as we don't have support for it's cpcap PMIC. I'll be posting regmap_spi based minimal cpcap patches later on for USB and the debug UART on droid 4 multiplexed with the USB connector. Cc: Marcel Partap <mpartap@gmx.net> Cc: Michael Scott <michael.scott@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
- Nov 10, 2016
-
-
Nishanth Menon authored
The DRA718-evm is a board based on TI's DRA718 processor targeting BOM-optimized entry infotainment systems and is a reduced pin and software compatible derivative of the DRA72 ES2.0 processor. This platform features: - 2GB of DDR3L - Dual 1Gbps Ethernet - HDMI, - uSD - 8GB eMMC - CAN - PCIe - USB3.0 - Video Input Port - LP873x PMIC More information can be found here[1]. Adding support for this board while reusing the data available in dra72-evm-common.dtsi. [1] http://www.ti.com/product/dra718 Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Lokesh Vutla authored
dra72-evm-common.dtsi consolidates dra72-evm.dts and dra72-evm-revc.dts which also include tps65917 pmic support as both the evms uses the same pmic. But, dra71-evm has mostly similar features with a different pmic. In order to exploit dra72-evm-common.dtsi, creating a separate dtsi for tps65915 support and including it in respective board files. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Lokesh Vutla authored
Add proper description of input voltage regulators and update the voltage rail map for all the regulators. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Lokesh Vutla authored
Pinmuxing for DRA7x/AM57x family of processors need to be done in IO isolation as part of initial bootloader executed from SRAM. This is done as part of iodelay configuration sequence and is required due to the limitations introduced by erratum ID: i869[1] (IO Glitches can occur when changing IO settings) and elaborated in the Technical Reference Manual[2] 18.4.6.1.7 Isolation Requirements. Only peripheral that is permitted for dynamic pin mux configuration is MMC and DCAN. MMC is permitted to change to accommodate the requirements for varied speeds (which require IO-delay support in kernel as well). DCAN is a result of i893[1] (DCAN initialization sequence). With the exception of DCAN and MMC, all other pin mux configurations are removed from the dts. [1] http://www.ti.com/lit/er/sprz436a/sprz436a.pdf [2] http://www.ti.com/lit/ug/spruhz7c/spruhz7c.pdf Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Yegor Yefremov authored
This change is needed in order to enable some hardware components from bootloader. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Keerthy authored
rtc can either be supplied from internal 32k clock or external crystal generated 32k clock. Internal clock is SoC specific and the external clock is board dependent. Assigning the corresponding clocks. Signed-off-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Yegor Yefremov authored
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Mugunthan V N authored
Add DMA properties for tscadc Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Mugunthan V N authored
Add DMA properties for tscadc Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
H. Nikolaus Schaller authored
Add USR1 button. Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
H. Nikolaus Schaller authored
Add LEDs. Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
H. Nikolaus Schaller authored
Add EEPROM. Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
This enables the power button driver gets corresponding IRQ number by using platform_get_irq(). Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
This enables the charger driver gets corresponding IRQ number by using platform_get_irq_byname() helper. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
AM335x bone based boards have the PMIC interrupt named NMI which is connected to TPS65217 device. AM335x main interrupt controller provides it and the number is 7. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
Support the power button driver and disable it by default. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
Support the charger driver and disable it by default. Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
Milo Kim authored
TPS65217 MFD driver supports the IRQ domain to handle the charger input interrupts and push button status event. The interrupt controller enables corresponding IRQ handling in the charger[*] and power button driver[**]. [*] drivers/power/supply/tps65217_charger.c [**] drivers/input/misc/tps65218-pwrbutton.c Signed-off-by: Milo Kim <woogyom.kim@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-
- Oct 03, 2016
-
-
Vladimir Zapolskiy authored
The change adds a new device node with description of generic SRAM on-chip memory found on NXP LPC32xx SoC series and connected to AHB matrix slave port 3. Note that NXP LPC3220 SoC has 128KiB of SRAM memory, the other LPC3230, LPC3240 and LPC3250 SoCs all have 256KiB SRAM space, in the shared DTSI file this change specifies 128KiB SRAM size. Also it's worth to mention that the SRAM area contains of 64KiB banks, 2 banks on LPC3220 and 4 banks on the other SoCs from the series, and all SRAM banks but the first one have independent power controls, the description of this feature will be added with the introduction of power domains for the SoC series. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Cc: Sylvain Lemieux <slemieux.tyco@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
-
- Sep 29, 2016
-
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /memory has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-
Jisheng Zhang authored
This patch fixes the following DTC warning with W=1: "Node /soc has a reg or ranges property, but no unit name" Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
-