- Feb 17, 2015
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Markos Chandras authored
The local_r4k_flush_cache_sigtramp function uses the 'cache' instruction inside an asm block. However, MIPS R6 changed the opcode for the cache instruction and as a result of which we need to set the correct ISA level. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
MIPS uses the cpu_has_mips_r2_exec_hazard macro to determine whether the EHB instruction is available or not. This is necessary for MIPS R6 which also supports the EHB instruction. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The MIPS R6 pref instruction only has 9 bits for the immediate field so skip the micro-assembler PREF instruction if the offset does not fit in 9 bits. Moreover, bit 30 (Pref_PrepareForStore) is no longer valid in MIPS R6, so we change the default for all MIPS R6 processors to bit 5 (Pref_StoreStreamed). Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
MIPS R6 dropped the unaligned load and store instructions so we need to re-write this part of the code for R6 to store one byte at a time. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
MIPS R6 does not support the unaligned load and store instructions so we add a special MIPS R6 case to copy one byte at a time if we need to read/write to unaligned memory addresses. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
The load/store unaligned instructions have been removed in MIPS R6 so we need to re-implement the related macros using the regular load/store instructions. Moreover, the load/store from coprocessor 2 instructions have been reallocated in Release 6 so we will handle them in the emulator instead. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The "addi" instruction will trap on overflows which is not something we need in this code, so we replace that with "addiu". Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00430.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Cc: Paul Burton <paul.burton@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The jr instruction opcode has changed in R6 so make sure the correct ISA level is set prior using that instruction. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add the MIPS R6 related preprocessor definitions for FPU signal related functions. MIPS R6 only has FR=1 so avoid checking that bit on the C0/Status register. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add the MIPS R6 related preprocessor definitions for save/restore FPU related functions. We also set the appropriate ISA level so the final return instruction "jr ra" will produce the correct opcode on R6. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add MIPS R6 support to cache and ftlb exceptions, as well as to the hwrena and ebase register configuration. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
Print 'mips64r6' and/or 'mips32r6' if the kernel is running on a MIPS R6 core. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The instruction hazard barrier in the form of: jr.hb ra nop is valid on MIPS R6 as well. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add MIPS R6 support when decoding the config0 c0 register. Also add MIPS R6 support when examining the ebase c0 register to get the core number and when getting the shadow set number from the srsctl c0 register. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Just like MIPS R2, in MIPS R6 it is possible to determine if a timer interrupt has happened or not. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
The current HW bugs checked in cpu-bugs64, do not apply to R6 cores and they cause compilation problems due to removed <R6 instructions, so do not check for them for the time being. Reviewed-by:
Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
"sub $reg, imm" is not a real MIPS instruction. The assembler can replace that with "addi $reg, -imm". However, addi has been removed from R6, so we replace the "sub" instruction with the "addiu" one. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the appropriate ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA level. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the opcodes for LL/SC instructions so we need to set the correct ISA. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
GCC versions supporting MIPS R6 use the ZC constraint to enforce a 9-bit offset for MIPS R6. We will use that for all MIPS R6 LL/SC instructions. Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The GCC_OFF12_ASM macro is used for 12-bit immediate constrains but we will also use it for 9-bit constrains on MIPS R6 so we rename it to something more appropriate. Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6, just like MIPS R2, have scratch pad storage, so add a new symbol which is selected by MIPS R2 and R6. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00389.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
MIPS R6 changed the 'cache' instruction opcode and reduced the offset field to 8 bits. This means we now have to adjust the base register every 256 bytes and as a result of which we can no longer use the previous cache functions. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
Add the MIPS R6 related definitions to the IRQ related macros Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
Add the MIPSR6 related definitions to MIPS hazards Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add MIPS R6 to the ISA definitions Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The following instructions have been removed from MIPS R6 ulw, ulh, swl, lwr, lwl, swr. However, all of them are used in the MIPS specific checksum implementation. As a result of which, we will use the generic checksum on MIPS R6 Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
The "add" instruction is actually a macro in binutils and depending on the size of the immediate it can expand to an "addi" instruction. However, the "addi" instruction traps on overflows which is not something we want on address calculation. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00121.html Cc: Paul Burton <paul.burton@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
EI/DI instructions are available in MIPS R6 so add the needed definitions. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
The HI/LO registers have been removed from MIPS R6. Instructions such as MULT and DIV have been replaced with a new pair of instructions for the HI/LO operations for example: MULT -> MUL, MUH DIV -> DIV, MOD So we avoid preserving the pre-R6 HI/LO registers in MIPS R6 Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Define the MODULE_PROC_FAMILY for the MIPS R6 ISA. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Markos Chandras authored
There are certain places where the code uses .set mips32 or .set mips64 or .set arch=r4000. In preparation of MIPS R6 support, and in order to use as less #ifdefs as possible, we define new macros to set similar annotations for MIPS R6. Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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- Feb 16, 2015
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Leonid Yegoshin authored
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
MIPS R6 redefines several instructions and reduces the immediate field to 9-bits so add related macros for the microassembler. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add build support for the latest revision (R6) of the MIPS ISA. microMIPS is not yet supported. Link: http://www.linux-mips.org/archives/linux-mips/2015-01/msg00386.html Cc: Maciej W. Rozycki <macro@linux-mips.org> Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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Leonid Yegoshin authored
Add a case in cpu_probe_mips for the MIPS generic QEMU processor ID. Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com>
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