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  1. Mar 07, 2014
    • Thomas Petazzoni's avatar
      ARM: mvebu: change the default PCIe apertures for Armada 370/XP · 46febc63
      Thomas Petazzoni authored
      
      
      The latest Marvell bootloaders for various boards change the MBus
      Window base address from 0xC0000000 to 0xF0000000, in order to make
      more RAM in the first 4 GB actually usable by the kernel (RAM that is
      covered by the MBus window is "shadowed" and therefore not usable).
      
      However, our default PCIe memory and I/O apertures where sitting at
      0xe0000000 (for memory) and 0xe8000000 (for I/O), which will now be
      outside of the MBus Window range on those platforms. To make things
      work, we have to ensure those apertures use addresses in the
      0xF0000000 -> 0xFFFFFFFF range.
      
      Of course this change of the MBus Window base address from 0xC0000000
      to 0xF0000000 also comes with a change of the internal register base
      address from 0xD0000000 to 0xF1000000.
      
      We have therefore designed the following memory map:
      
       * 0xF0000000 -> 0xF1000000: 16 MB, used for NOR flashes on Armada XP
         GP and Armada XP DB.
      
       * 0xF1000000 -> 0xF1100000: 1 MB, used for internal registers.
      
       * 0xF8000000 -> 0xFFE00000: 126 MB, used for PCIe memory.
      
       * 0xFFE00000 -> 0xFFF00000: 1 MB, used for PCIe I/O.
      
       * 0xFFF00000 -> 0xFFFFFFFF: 1 MB, used for the BootROM mapping
      
      There is one exception to this layout: the Armada XP OpenBlocks, which
      has a 128 MB NOR flash, mapped from 0xF0000000 to 0xF8000000. This
      does not conflict with the current change for the PCIe I/O and memory
      apertures, and continues to work because on Armada XP OpenBlocks, the
      bootloader is an old one, and continues to have internal registers
      mapped at 0xD0000000.
      
      Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
      Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
      46febc63
  2. Mar 04, 2014
  3. Feb 23, 2014
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  10. Feb 03, 2014
    • Linus Torvalds's avatar
      Linus 3.14-rc1 · 38dbfb59
      Linus Torvalds authored
      38dbfb59
    • Linus Torvalds's avatar
      Merge branch 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux · 69048e01
      Linus Torvalds authored
      Pull parisc updates from Helge Deller:
       "The three major changes in this patchset is a implementation for
        flexible userspace memory maps, cache-flushing fixes (again), and a
        long-discussed ABI change to make EWOULDBLOCK the same value as
        EAGAIN.
      
        parisc has been the only platform where we had EWOULDBLOCK != EAGAIN
        to keep HP-UX compatibility.  Since we will probably never implement
        full HP-UX support, we prefer to drop this compatibility to make it
        easier for us with Linux userspace programs which mostly never checked
        for both values.  We don't expect major fall-outs because of this
        change, and if we face some, we will simply rebuild the necessary
        applications in the debian archives"
      
      * 'parisc-3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux:
        parisc: add flexible mmap memory layout support
        parisc: Make EWOULDBLOCK be equal to EAGAIN on parisc
        parisc: convert uapi/asm/stat.h to use native types only
        parisc: wire up sched_setattr and sched_getattr
        parisc: fix cache-flushing
        parisc/sti_console: prefer Linux fonts over built-in ROM fonts
      69048e01
    • Mikulas Patocka's avatar
      hpfs: optimize quad buffer loading · 1c0b8a7a
      Mikulas Patocka authored
      
      
      HPFS needs to load 4 consecutive 512-byte sectors when accessing the
      directory nodes or bitmaps.  We can't switch to 2048-byte block size
      because files are allocated in the units of 512-byte sectors.
      
      Previously, the driver would allocate a 2048-byte area using kmalloc,
      copy the data from four buffers to this area and eventually copy them
      back if they were modified.
      
      In the current implementation of the buffer cache, buffers are allocated
      in the pagecache.  That means that 4 consecutive 512-byte buffers are
      stored in consecutive areas in the kernel address space.  So, we don't
      need to allocate extra memory and copy the content of the buffers there.
      
      This patch optimizes the code to avoid copying the buffers.  It checks
      if the four buffers are stored in contiguous memory - if they are not,
      it falls back to allocating a 2048-byte area and copying data there.
      
      Signed-off-by: default avatarMikulas Patocka <mikulas@artax.karlin.mff.cuni.cz>
      Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
      1c0b8a7a