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  1. Oct 07, 2016
    • Paul Burton's avatar
      MIPS: Adjust MIPS64 CAC_BASE to reflect Config.K0 · 3ffc17d8
      Paul Burton authored
      
      
      On MIPS64 we define the default CAC_BASE as one of the xkphys regions of
      the virtual address space. Since the CCA is encoded in bits 61:59 of
      xkphys addresses, fixing CAC_BASE to any particular one prevents us from
      dynamically changing the CCA as we do for MIPS32 where CAC_BASE is
      placed within kseg0. In order to make the kernel more generic, drop the
      current kludge that gives CAC_BASE CCA=3 if CONFIG_DMA_NONCOHERENT is
      selected (disregarding CONFIG_DMA_MAYBE_COHERENT) & CCA=5 (which is not
      standardised by the architecture) otherwise. Instead read Config.K0 and
      generate the appropriate offset into xkphys, presuming that either the
      bootloader or early kernel code will have configured Config.K0
      appropriately. This seems like the best option for a generic
      implementation.
      
      The ip27 spaces.h is adjusted to set its former value of CAC_BASE, since
      it's the only user of CAC_BASE from assembly (in its smp_slave_setup
      macro). This allows the generic case to focus solely on C code without
      breaking ip27.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14351/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      3ffc17d8
    • Paul Burton's avatar
      MIPS: Print CM error reports upon bus errors · dabdc185
      Paul Burton authored
      
      
      If a bus error occurs on a system with a MIPS Coherence Manager (CM)
      then the CM may hold useful diagnostic information. Printing this out
      has so far been left up to boards, with the requirement that they
      register a board_be_handler function & call mips_cm_error_decode() from
      there.
      
      In order to avoid boards other than Malta needing to duplicate this
      code, call mips_cm_error_decode() automatically if the board registers
      no board_be_handler, and remove the Malta implementation of that.
      
      This patch results in no functional change, but removes a further piece
      of platform-specific code.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14350/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      dabdc185
    • Paul Burton's avatar
      MIPS: Support per-device DMA coherence · 20d33064
      Paul Burton authored
      
      
      On some MIPS systems, a subset of devices may have DMA coherent with CPU
      caches. For example in systems including a MIPS I/O Coherence Unit
      (IOCU), some devices may be connected to that IOCU whilst others are
      not.
      
      Prior to this patch, we have a plat_device_is_coherent() function but no
      implementation which does anything besides return a global true or
      false, optionally chosen at runtime. For devices such as those described
      above this is insufficient.
      
      Fix this by tracking DMA coherence on a per-device basis with a
      dma_coherent field in struct dev_archdata. Setting this from
      arch_setup_dma_ops() takes care of devices which set the dma-coherent
      property via device tree, and any PCI devices beneath a bridge described
      in DT, automatically.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14349/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      20d33064
    • Paul Burton's avatar
      MIPS: dma-default: Don't check hw_coherentio if device is non-coherent · cfa93fb9
      Paul Burton authored
      
      
      There are no cases where plat_device_is_coherent() will return zero
      whilst hw_coherentio is non-zero, and acting any differently in such a
      case doesn't make much sense - if a device is non-coherent with the CPU
      caches then access to memory "coherent" with DMA must be uncached. Clean
      up the nonsensical case.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14348/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      cfa93fb9
    • Paul Burton's avatar
      MIPS: Sanitise coherentio semantics · f2302023
      Paul Burton authored
      
      
      The coherentio variable has previously been used as a boolean value,
      indicating whether the user specified that coherent I/O should be
      enabled or disabled. It failed to take into account the case where the
      user does not specify any preference, in which case it makes sense that
      we should default to coherent I/O if the hardware supports it
      (hw_coherentio is non-zero).
      
      Introduce an enum to clarify the 3 different values of coherentio & use
      it throughout the code, modifying plat_device_is_coherent() &
      r4k_cache_init() to take into account the default case.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Cc: Paul Burton <paul.burton@imgtec.com>
      Patchwork: https://patchwork.linux-mips.org/patch/14347/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      f2302023
    • Paul Burton's avatar
      MIPS: PCI: Support generic drivers · 87dd9a4d
      Paul Burton authored
      
      
      Introduce support for PCI drivers using only functionality provided
      generically by the PCI subsystem, by adding the minimum arch-provided
      functions required.
      
      The driver this has been developed for & tested with the xilinx-pcie on
      a MIPS Boston development board.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14346/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      87dd9a4d
    • Paul Burton's avatar
      MIPS: PCI: Introduce CONFIG_PCI_DRIVERS_LEGACY · c5611df9
      Paul Burton authored
      
      
      Introduce 2 Kconfig symbols, CONFIG_PCI_DRIVERS_GENERIC &
      CONFIG_PCI_DRIVERS_LEGACY, which indicate whether the system should be
      built to for PCI drivers using the MIPS-specific struct pci_controller
      API (hereafter "legacy" drivers) or more generic drivers using only
      functionality provided by the PCI core (hereafter "generic" drivers).
      
      The Kconfig entries are created such that platforms have to select
      CONFIG_PCI_DRIVERS_GENERIC if they wish to use it - that is, the default
      is CONFIG_PCI_DRIVERS_LEGACY so that existing platforms need no
      modification.
      
      The functions declared in pci.h are rearranged with those provided only
      by pci-legacy.c being guarded by an #ifdef CONFIG_PCI_DRIVERS_LEGACY to
      ensure they are only used in configurations where they are implemented.
      
      Signed-off-by: default avatarPaul Burton <paul.burton@imgtec.com>
      Cc: linux-mips@linux-mips.org
      Patchwork: https://patchwork.linux-mips.org/patch/14345/
      
      
      Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
      c5611df9
  2. Oct 06, 2016
  3. Oct 05, 2016