- Sep 30, 2013
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Sebastian Hesselbarth authored
This adds an initial DT file for the Globalscale D3Plug with Dove SoC. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a node for the pcie controllers found on Dove SoCs to the SoC DT include. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
With mbus node in place, now relocate all internal device nodes to internal-regs node with proper address ranges. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a MBus node including ranges and pcie apertures required later. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This adds a macro used for defining address window's target ID and attribute cells for the MBus ranges entry. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Sebastian Hesselbarth authored
This coverts Dove DT board files to preprocessor includes instead of dtc includes. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
This commit adjusts the Armada 370 and Armada XP PCIe controllers Device Tree informations to reference their MSI controller. In the case of this platform, the MSI controller is implemented by the MPIC. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
Adds the 'msi-controller' property to the main interrupt controller Device Tree node, to indicate that it can now behave as a MSI controller. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Tested-by: Daniel Price <daniel.price@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Sep 18, 2013
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Gregory CLEMENT authored
The mv64xxx-i2c embedded in the Armada XP have a new feature to offload i2c transaction. This new version of the IP come also with some errata. This lead to the introduction to a another compatible string. This commit split the i2c information into armada-370.dtsi and armada-xp.dtsi. Most of the data remains the same and stay in the common file Armada-370-xp.dtsi. With this new feature the size of the registers are bigger for Armada XP and the new compatible string is used. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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- Sep 13, 2013
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Maxime Ripard authored
The A20-olinuxino-micro has the EMAC wired in. Enable it in the DT so that we can use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The Cubieboard2, just like its A10 counterpart, has the Ethernet wired in. Enable it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The A20 has several muxing options for the EMAC. Yet, the currently supported boards only use one set of them. Add that pin set to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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Maxime Ripard authored
The Allwinner A20 SoC also have the EMAC found on the A10 and A10s. Enable the support for it in the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Sep 07, 2013
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Tomasz Figa authored
Since pwm-samsung bindings require at least one clock to be specified, this patch adds the missing clocks and clock-names properties to specify clocks used by PWM block on Exynos4 SoCs. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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- Sep 03, 2013
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Laurent Pinchart authored
Replace the numerical polarity flags with the PWM_POLARITY_INVERTED symbolic constant. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
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- Aug 31, 2013
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Jon Medhurst (Tixy) authored
The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is needed to get Multi-Cluster Power Management (MCPM) working. Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Aug 30, 2013
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Dinh Nguyen authored
"dw-apb-timer-osc" and "dw-apb-timer-sp" are the same implementation of the DW APB timer, just fed by different clocks. Thus, deprecate both "dw-apb-timer-osc" and "dw-apb-timer-sp" in lieu of "dw-apb-timer". Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Reviewed-by: Pavel Machek <pavel@denx.de> Acked-by: Stephen Warren <swarren@wwwdotorg.org> CC: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ian.campbell@citrix.com> CC: Arnd Bergmann <arnd@arndb.de> Cc: Olof Johansson <olof@lixom.net> CC: Jamie Iles <jamie@jamieiles.com> Cc: John Stultz <john.stultz@linaro.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Pavel Machek <pavel@denx.de> Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Olof Johansson <olof@lixom.net> v3: - Split out a separate that cleans up the timer entries and clock information. - Clearly states which binding is deprecated in the bindings doc. v2: - Deprecate the "dw-apb-timer-osc" and "dw-apb-timer-sp" but maintain backwards compatibility in the driver.
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Boris BREZILLON authored
Fix phy0 address to match the reg property defined in phy0 node. Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- Aug 29, 2013
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Stephen Boyd authored
Let's follow the ratified DT binding and use uartdm instead of hsuart. This does break backwards compatibility but this shouldn't be a problem because the uart driver isn't probing on these devices without adding clock support (which isn't merged so far). Cc: David Brown <davidb@codeaurora.org> Acked-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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- Aug 28, 2013
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Sebastian Andrzej Siewior authored
So I assumed that Beagle bone has only one USB port in host mode because the micro USB connector had an USB-UART there. I was wrong a little. The second port runs on host mode, but the micro USB plug is connected to an internal HUB with two ports: one to the USB-UART and one to musb instance one. For that reason, this patch enables both ports: the primary in device mode only and the second in host mode only. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
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Sebastian Andrzej Siewior authored
This is what I observe: On the first connect, the musb starts with DEVCTL.Session set. On disconnect, musb_core calls try_idle. That functions removes the Session bit signalizing that the session is over (something that only in OTG is required). A new device, that is plugged, is no longer recognized. I've setup a timer and checked the DEVCTL register and I haven't seen a change in VBus and I saw the B-Device bit set. After setting the IDDIG into A mode and forcing the device to behave like a A device, I didn't see a change. Neither VBUS goes to 0b11 nor does a session start request comes. In the TI-v3.2 kernel they skip to call musb_platform_try_idle() in the OTG_STATE_A_WAIT_BCON state while not in OTG mode. Since the second port hast a standard A plug the patch changes the port to run in host mode only and skips the timer which would remove DEVCTL.Session so we can reconnect to another device later. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
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Sebastian Andrzej Siewior authored
This relfects the code and dts requires changes due to recent .dts binding updates: - use mg prefix for the Metor Graphics specific attributes - use power in mA not in mA/2 as specifed in the USB2.0 specification - remove the child node for USB. This is driver specific on won't be reflected in the device tree - use the "mentor" prefix instead of "mg". - use "dr_mode" istead of "mg,port-mode" for the port mode. The former is used by a few other drivers. Cc: Rob Herring <rob.herring@calxeda.com> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Ian Campbell <ian.campbell@citrix.com> Cc: devicetree@vger.kernel.org Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
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Sebastian Andrzej Siewior authored
I forgot to separete the different names in the reg-names property. This didn't cause anything to fail because the driver does not use the names and simply relies on the order of the memory offsets in reg. This patch fixes this in case it is used later. Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de> Signed-off-by: Felipe Balbi <balbi@ti.com>
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- Aug 27, 2013
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Boris BREZILLON authored
This patch describe the phy used on atmel sama5d3 mother board: - phy address - phy interrupt pin Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- Aug 26, 2013
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Maxime Ripard authored
Now that the clock driver knows about the available clocks found on the A20, we can build up the clock tree from the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
Now that the clock driver has support for the A31 clocks, we can add them to the DTSI and start using them in the relevant hardware blocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Maxime Ripard authored
The A10s has only a subset of the A10 gates. Now that the clock driver has support for this gates set, switch to it in the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Emilio López <emilio@elopez.com.ar>
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Naveen Krishna Chatradhi authored
Add ADC device tree node for exynos5420 and exynos5250 Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Vikas Sajjan authored
Adds RTC DT node to Exynos5420 SoC Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Vikas Sajjan authored
Moves the RTC DT node's "status" property from exynos5250 board (arndale & snow) dts files to exynos5250.dtsi, since the bindings in exynos5250.dtsi depicts the RTC h/w completely. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Vikas Sajjan authored
Fixes the RTC DT node name for Exynos5250 as per the DT node naming convention. Signed-off-by: Vikas Sajjan <vikas.sajjan@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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- Aug 23, 2013
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Qipan Li authored
the old codes defined uart0_nostreamctrl_pins, but missed pingroup and padmux definition for it. this patch fixes it. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Josh Wu authored
Signed-off-by: Josh Wu <josh.wu@atmel.com>
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Josh Wu authored
Signed-off-by: Josh Wu <josh.wu@atmel.com>
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Josh Wu authored
The NFC driver code doesn't use atmel,has-nfc and atmel,use-nfc-sram. Signed-off-by: Josh Wu <josh.wu@atmel.com>
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- Aug 22, 2013
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Jingchang Lu authored
enable i2c0 device on Vybrid VF610 Tower Board Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Alexander Shiyan authored
This adds one more I2C2 alternate pinmux entry. GPIO1_2 <=> SCL GPIO1_3 <=> SDA Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Alexander Shiyan authored
This unmix module/pin definitions and reduce indentation for pin groups, so makes template a bit cleaner. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Peter Chen authored
USB OTG vbus pin needs to be configured as gpio function at sabresd board. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Peter Chen authored
We enabled USB host 1, so host 1's vbus should be on to let host 1 work. Signed-off-by: Peter Chen <peter.chen@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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