- Aug 19, 2017
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Chen-Yu Tsai authored
The BPI-M3 is an Allwinner A83T based SBC in the Bananapi/Bpi family. It is roughly the same form factor as the BPI-M1+, with roughly the same peripherals and connectors: - 2GB LPDDR3 DRAM - 8GB eMMC - Micro-SD card slot - HDMI output - Headset (stereo + mic) jack - Onboard mic - Gigabit Ethernet with RTL8211E transceiver - Ampak AP6212 WiFi + BT - USB OTG connector - USB-to-SATA bridge connected through a USB 2.0 hub - Consumer IR receiver - MIPI DSI LCD panel connector - Camera interface (parallel and MIPI CSI) connector - 3 LEDs (Red, Green, Blue), of which 2 are controllable (GB) - Raspberry Pi 2 compatible GPIO header Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
The h8homlet board has the A83T's standard USB 1.1/2.0 host pair routed to a USB host port on the board. The other USB host port is routed to USB OTG controller. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
The Cubietruck-plus has a GL830 USB-to-SATA bridge connected to EHCI0, and a USB3503 HSIC USB 2.0 hub connected to EHCI1. The USB3503's I2C control interface is not connected. This patch enables both EHCI controllers, adds a device node for the USB hub, and includes sunxi-common-regulators.dtsi for the VBUS regulators. The existing reg_vcc3v3 is dropped as it is also available in the set of common regulators. Other unused regulators are disabled. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
The USB OTG controller found on the A83T is compatible with the one found on the A33. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
The A83T has 3 USB PHYs, 1 for USB OTG, 1 for standard USB 2.0, 1 for USB HSIC. EHCI0/OHCI0 are the standard USB host pair, while EHCI1 is the host controller for HSIC. OTG is not added yet. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- Aug 08, 2017
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Chen-Yu Tsai authored
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch adds the device nodes for the AC100 chip to the h8homlet-v2 device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch enables the RSB controller and adds a device node for the PMIC die to the h8homlet-v2 device tree. Since the AXP813 and AXP818 are virtually identical, this patch uses the compatible string for the former as a fallback. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch adds the device nodes for the AC100 chip to the Cubietruck Plus device tree. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The AXP813/AXP818 PMICs used with the A83T/H8 SoCs are actually 2 dies in one package sharing the serial bus (I2C/RSB) pins. One die is the actual PMIC. The other is an AC100 codec / RTC combo chip. This patch enables the RSB controller and adds a device node for the PMIC die to the Cubietruck Plus device tree. Since the AXP813 and AXP818 are virtually identical, this patch uses the compatible string for the former as a fallback. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The A83T has an RSB controller for talking to the PMIC and audio codec. Add a device node for it. Since there is only one usable pinmux setting, for it, add that as well. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- Aug 05, 2017
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Chen-Yu Tsai authored
The H8 homlet has a micro-SD card slot connected to mmc0, and onboard eMMC from FORESEE, connected to mmc2. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
Now that we support the MMC controllers on the A83T SoC, we can enable them on some boards. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
mmc2 can support 8-bit eMMC chips, with a dedicated reset line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
The A83T has 3 MMC controllers. The third one is a bit special, as it supports a wider 8-bit bus, and a "new timing mode". Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Marcus Cooper authored
The dwmac-sun8i hardware is present on the Beelink X2. It uses the internal PHY. This patch create the needed emac node. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Fixed typo in commit subject] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Marcus Cooper authored
This STB has a type A socket which acts as OTG. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Maxime Ripard authored
The Bananapi M2-Magic is a board with an A33, a USB host and USB OTG connectors, and 8GB eMMC, an AP6212 WiFi/Bluetooth chip and connectors for DSI, CSI and GPIOs. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Correct subject prefix case] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Alexander Syring authored
The Cubietruck has an AXP209 PMIC with battery connector. This enables the battery power supply subnode. Signed-off-by: Alexander Syring <alex@asyring.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Correct subject prefix order] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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Chen-Yu Tsai authored
The R_INTC interrupt controller handles the NMI interrupt pin for the SoC. While there is no documentation or code from the vendor for this device on the A83T, existing mainline kernel drivers and bindings show this to be similar to the old Allwinner interrupt controller found on the A10 SoC, but with only the NMI interrupt wired. Register poking experiments confirm this. The device seems to be the same across all recent Allwinner SoCs, apart from the A20 and A80, which have a separate set of registers to handle the NMI interrupt. We already have a set of bindings supporting this on the A31. Add a device node for it, with an SoC specific compatible. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
We introduced a new compatible for the NMI or R_INTC interrupt controller. This new compatible has the register region aligned to the boundary listed in the SoC's memory map. This patch converts the NMI/R_INTC node to using the new compatible, and fixes up the register region and device node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Chen-Yu Tsai authored
We introduced a new compatible for the NMI or R_INTC interrupt controller. This new compatible has the register region aligned to the boundary listed in the SoC's memory map. This patch converts the NMI/R_INTC node to using the new compatible, and fixes up the register region and device node name. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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- Jul 27, 2017
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Chen-Yu Tsai authored
Now that the CCU device tree binding headers have been merged, we can use the properly named macros in the device tree, instead of raw numbers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Corentin Labbe authored
The datasheet said that emac register size is 0x10000 not 0x104 Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Fixed commit subject prefix] Signed-off-by: Chen-Yu Tsai <wens@csie.org>
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- Jul 02, 2017
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Maxime Ripard authored
This reverts commits 2c0cba48 ("arm: sun8i: sunxi-h3-h5: Add dt node for the syscon control module") to 2428fd0f ("arm64: defconfig: Enable dwmac-sun8i driver on defconfig") and 3432a86e ("arm: sun8i: orangepipc: use internal phy-mode") to 5a79b4f2 ("arm: sun8i: orangepi-2: use internal phy-mode") that should be merged through the arm-soc tree, and end up in merge conflicts and build failures. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- Jun 30, 2017
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LABBE Corentin authored
Since the PHY used is internal, simply set phy-mode as internal. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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LABBE Corentin authored
Since the PHY used is internal, simply set phy-mode as internal. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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LABBE Corentin authored
Since the PHY used is internal, simply set phy-mode as internal. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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LABBE Corentin authored
Since the PHY used is internal, simply set phy-mode as internal. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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LABBE Corentin authored
Since the PHY used is internal, simply set phy-mode as internal. Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- Jun 23, 2017
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Dinh Nguyen authored
Use 'clock-frequency' binding for the i2c node that will put the I2C driver into the standard operating mode. 'speed-mode' was not a valid binding for the I2C driver, remove it. Signed-off-by: Alan Tull <atull@kernel.org> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Marek Vasut authored
Add DT alias for the second ethernet present on mainboard rev 1.10. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Marek Vasut authored
Drop the LED node from VINing FPGA DT because the LED wiring is different on each mainboard revision. This wiring is therefore handled in mainboard DT Overlays. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Marek Vasut authored
Remove the EEPROMs attached to the I2C expander ports which lead to the backplane slots from the main VIN|ING DTS file. These EEPROMs are bound using separate DTO files, which lets us handle both two-slot and six-slot configuration of the backplane. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Marek Vasut authored
Enable the QSPI node and add the flash chips. Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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Marek Vasut authored
The ethernet block clock phandle must point to the clock node which represents the clock which directly supply the ethernet block. This is emac_x_clk , not emacx_clk , so fix this. From: Pavel Machek <pavel@denx.de> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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- Jun 21, 2017
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Viresh Kumar authored
Compiling the DT file with W=1, DTC warns like follows: Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a unit name, but no reg property Fix this by replacing '@' with '-' as the OPP nodes will never have a "reg" property. Reported-by: Krzysztof Kozlowski <krzk@kernel.org> Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Suggested-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
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- Jun 20, 2017
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Kishon Vijay Abraham I authored
commit 94647a30 ("ARM: dts: omap3-overo: Enable WiFi/BT combo") while enabling WiFi/BT combo added regulator to trigger the nReset signal of the Bluetooth module in vqmmc-supply. However BT should be handled by UART. Moreover "vqmmc" is not a defined binding for omap_hsmmc. While "vqmmc" in mmc2 hasn't caused any issues so far, mmc2 will start to mis-behave once omap_hsmmc defines "vqmmc" binding. Remove "vqmmc-supply" property in mmc2 here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Andreas Färber authored
Add Smart Power System node for PM domains. Signed-off-by: Andreas Färber <afaerber@suse.de>
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Andreas Färber authored
Use a custom S500 enable-method for all CPUs. Signed-off-by: Andreas Färber <afaerber@suse.de>
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- Jun 19, 2017
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Andreas Färber authored
Add Device Trees for Actions Semiconductor S500 SoC and LeMaker Guitar SoM and base board. Signed-off-by: Andreas Färber <afaerber@suse.de>
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