The STMicrolectornics's STM32F429 MCU has the following main features:
 - Cortex-M4 core running up to @180MHz
 - 2MB internal flash, 256KBytes internal RAM
 - FMC controller to connect SDRAM, NOR and NAND memories
 - SD/MMC/SDIO support
 - Ethernet controller
 - USB OTFG FS & HS controllers
 - I2C, SPI, CAN busses support
 - Several 16 & 32 bits general purpose timers
 - Serial Audio interface
 - LCD controller

Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>

Update the arria10 gmac nodes with all the necessary properties for ethernet
to function on the Arria10 devkit.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>

The Mele A1000G-quad and the Mele M9 have the same PCB, sofar we've been using
the same dts for both models. Unfortunately this does not work for the otg
controller, on the M9 this is routed to a micro-usb connector on the outside,
while as on the A1000G-quad it is connected to an usb to sata bridge
(which is not populated on the M9 pcb).

This commit adds a new dts for the Mele-A1000G-quad to allow using
different otg controller settings on the 2 boards.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The ga10h is an 10" tablet with an A33 or A23 soc, 1G RAM, 8G or 16G nand,
sdio wifi, 2 micro usb ports, 1 otg and 1 host and 1 micro sd slot.

This commit adds a dts file for the v1.1 pcb with an a33 soc.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The SinA33 is a core/SDK development board by Sinlinx. The core board
does not have any connectors or pads, other than the pads used to connect
it to the SDK board.

The core board only has the A33 SoC, 2 RAM chips, an eMMC flash chip,
the AXP223 PMIC, and supporting discrete components. eMMC is optional.

The SDK board has a USB host, USB OTG, volume control and home buttons,
audio input/output jacks, a micro-SD slot, camera and SDIO expansion
headers, an LCD connector, and a GPIO expansion header, which has
UARTs, MIPI DSI and I2C available. Only UART0 is enabled though.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The A33 adds an additional pinmux option for uart0 on the PB pins.
This was not present on the A23. Nor is it available on the H3,
which does not have the PB pingroup.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

mmc2 is mostly used with eMMC flash chips, as an alternative to
raw NAND flash chips. 8 bit mmc is commonly used.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The SOCrates has three HPS LEDs that can be turned on/off via gpio.
Use the first one has heartbeat and add the other two as free LEDs.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Enable the gpio0+1 controller.

Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add a dts node for the A9 SCU on the Arria10 platform.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>

Add an usb_clk node for a23/a33.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>

ET-Q8_A33 is A33 based cheap tablet in common Q8 format.

It has 512MB RAM, 4GB Nand, 7" Display, RDA5900P wifi, GSL1680 touch, etc.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>

Add a dtsi file for use with a33 based boards based on the new
sun8i-a23-a33.dtsi file.

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>

Rename sun8i-a23.dtsi to sun8i-a23-a33.dtsi as the base dtsi for the A33
is 99% the same and add a new sun8i-a23.dtsi including sun8i-a23-a33.dtsi
and setting the few things not shared with the A33 (mbus-clk, pio
compatible and interrupts).

Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Chen-Yu Tsai <wens@csie.org>

The A20 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>

The A10s and A13 have a few SRAM that can be mapped either to a device or
to the CPU, with the mapping being controlled by a SRAM controller.

Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>

The A10 has a few SRAM that can be mapped either to a device or to the CPU,
with the mapping being controlled by a SRAM controller.

Add the SRAM controller, the SRAM that it drives and the section that can
be used by the various devices.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>

This patch reverts commit ccb4ada2 ("ARM: dts: sun7i: Add A20 SRAM and
SRAM controller"), commit e6f51e4b ("ARM: dts: sun5i: Add A13 and A10s
SRAM and SRAM controller") and commit 6d92b80f

 ("ARM: dts: sun4i: Add
A10 SRAM and SRAM controller").

The bindings have been changed in the SRAM driver, and we need to
change the DT accordingly.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

On A80 there are 2 watchdogs, one in the main block, and one in the
R (special) block. We do not have information on the R block watchdog,
other than the register layout is the same, and the interrupt number.
Both are able to reset the whole system.

Add the main watchdog, in case the R block is used for special purposes
like running an RTOS.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The BananaPro uses uart4 for the default rx/tx pins on the 40 pins connector,
so enable uart4.

Uart2 is also available at the bananapro io-pins, but like on the bananapi
the primary function of the pins is to act as gpios, see:
http://forum.lemaker.org/forum.php?mod=viewthread&tid=10852



Remove the uart2 node, people who want to use uart2 can do so with a
devicetree-overlay.

Signed-off-by: Michael Ring <mail@michael-ring.org>
[hdegoede@redhat.com: Remove uart2 node]
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux
entry for these.

Signed-off-by: Michael Ring <mail@michael-ring.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

The A23 Evaluation Board has an MMC slot, two UARTs, NAND, a few display
connectors (RGB, MIPI, LVDS), a mini-PCIE slot, USB host and OTG and a
bunch of embedded sensors.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

Fix indentation nits to make mt8173.dtsi more consistent.

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

Use the new zynq binding for macb ethernet, since it will disable half
duplex gigabit like the Zynq TRM says to do. Also allow the compatible
cadence gem binding that won't disable half duplex but works otherwise.

Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

parallella - Remove linux,stdout-path.
Use stdout-path to identify kernel console

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>

Add missing alias node.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>

The NAND controller is a child node of the UBUS (legacy) bus, not the
AXI (new) bus, re-parent the NAND controller node accordingly. This was
a mistake introduced by a failed merge of this NAND node with other
changes (PMB).

Fixes: b5762cac

 ("ARM: bcm63138: add NAND DT support")
Reported-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>

Use the new compatible introduced in order to benefit of a wider and
more accurate range of baud rates to be used.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

DNS-327L is a 2-bay NAS with the following specs:
     - 512MiB RAM
     - 128MiB NAND Flash
     - 1 GbE interface (Marvell PHY)
     - 1 rear USB 3.0 port (via PCIe USB 3.0 controller)
     - 2 internal SATA ports handled by the Armada 370:
       	 uses 2 gpios for power control
     - two front 2-color leds (amber + white) for both discs,
        controlled by the SoC
     - One white LED handled by SoC (USB)
     - 3 buttons. Power handled by weltrend, USB and
       RESET (on the bottom) are wired via GPIOs
     - Unidentified i2c device at address 0x13 (via i2cdetect)
     - UART0 providing serial console
     - Weltrend MCU serving for RTC, temperature, fan control,
       and power button handling interfaced via UART1
       (Handled via userspace dns320l-daemon)

Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Add DMA properties to all SCIF, SCIFA, SCIFB, and HSCIF device nodes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add DMA properties to all SCIF, SCIFA, SCIFB, and HSCIF device nodes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Add DMA properties to all SCIF, SCIFA, SCIFB, and HSCIF device nodes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Starting with commit 8947e396

 ("Documentation: dt: mtd: replace
"nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor"
binding indicating support for JEDEC identification.

Use it for all flashes that are supposed to support READ ID op according
to the datasheets.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Starting with commit 8947e396

 ("Documentation: dt: mtd: replace
"nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor"
binding indicating support for JEDEC identification.

Use it for all flashes that are supposed to support READ ID op according
to the datasheets.

Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This patch adds support for the Linksys WRT1200AC (Caiman) and
the Linksys WRT1900AC v2 (Cobra).

Both boards have:

- 2 Marvell 88W8864 radios
- 1 USB 3.0 port
- 1 USB 2.0/eSATAp port
- 2 Ethernet interfaces connected to a 88E6176 switch (1x WAN + 4x LAN)
- 128MB NAND flash
- 512MB RAM

gregory.clement@free-electrons.com: use serial0:115200n8 in
stdout-path and remove the bootargs part in the chosen node

Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Tested-by: Keita Kobayashi <keita.kobayashi.ym@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This board is based on Juno r0 with updated Cortex A5x revisions
and board errata fixes. It also contains coherent ThinLinks ports
on the expansion slot that allow for an AXI master on the daughter
card to participate in a coherency domain.

Support for SoC PCIe host bridge will be added as a separate series.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Acked-by: Jon Medhurst <tixy@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>

Juno contains a GICv2m extension for handling PCIe MSI messages.
Add a node declaring the first frame of the extension.

Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
Acked-by: Jon Medhurst <tixy@linaro.org>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>