Skip to content
  1. Sep 04, 2021
  3. Sep 02, 2021
    • Stephen Boyd's avatar
      Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next · 47505bf3
      Stephen Boyd authored 
      * clk-kirkwood:
  clk: kirkwood: Fix a clocking boot regression

* clk-imx:
  clk: imx8mn: Add M7 core clock
  clk: imx8m: fix clock tree update of TF-A managed clocks
  clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate
  clk: imx8mn: use correct mux type for clkout path
  clk: imx8mm: use correct mux type for clkout path

* clk-doc:
  dt-bindings: clock: samsung: fix header path in example
  MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry
  dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos AudSS to dtschema
  dt-bindings: clock: samsung: convert Exynos4 to dtschema
  dt-bindings: clock: samsung: convert Exynos3250 to dtschema
  dt-bindings: clock: samsung: convert Exynos542x to dtschema
  dt-bindings: clock: samsung: add bindings for Exynos external clock
  dt-bindings: clock: samsung: convert Exynos5250 to dtschema
  dt-bindings: clock: brcm,iproc-clocks: fix armpll properties
  clk: zynqmp: Fix kernel-doc format
  clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings
  clk: zynqmp: fix kernel doc

* clk-zynq:
  clk: zynqmp: Fix a memory leak
  clk: zynqmp: Check the return type

* clk-ralink:
  clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates
      47505bf3
    • Stephen Boyd's avatar
      Merge branches 'clk-nvidia', 'clk-rockchip', 'clk-at91' and 'clk-vc5' into clk-next · 8fb59ce1
      Stephen Boyd authored 
       - Support the SD/OE pin on IDT VersaClock 5 and 6 clock generators

* clk-nvidia:
  clk: tegra: fix old-style declaration
  clk: tegra: Remove CLK_IS_CRITICAL flag from fuse clock
  soc/tegra: fuse: Enable fuse clock on suspend for Tegra124
  soc/tegra: fuse: Add runtime PM support
  soc/tegra: fuse: Clear fuse->clk on driver probe failure
  soc/tegra: pmc: Prevent racing with cpuilde driver
  soc/tegra: bpmp: Remove unused including <linux/version.h>

* clk-rockchip:
  clk: rockchip: make rk3308 ddrphy4x clock critical
  clk: rockchip: drop GRF dependency for rk3328/rk3036 pll types
  dt-bindings: clk: Convert rockchip,rk3399-cru to DT schema
  clk: rockchip: Add support for hclk_sfc on rk3036
  clk: rockchip: rk3036: fix up the sclk_sfc parent error
  clk: rockchip: add dt-binding clkid for hclk_sfc on rk3036

* clk-at91:
  clk: at91: clk-generated: Limit the requested rate to our range

* clk-vc5:
  clk: vc5: Add properties for configuring SD/OE behavior
  clk: vc5: Use dev_err_probe
  dt-bindings: clk: vc5: Add properties for configuring the SD/OE pin
      8fb59ce1
    • Stephen Boyd's avatar
      Merge branch 'clk-frac-divider' into clk-next · 1faa7cb2
      Stephen Boyd authored 
       - Add power of two flag to fractional divider clk type

* clk-frac-divider:
  clk: fractional-divider: Document the arithmetics used behind the code
  clk: fractional-divider: Introduce POWER_OF_TWO_PS flag
  clk: fractional-divider: Hide clk_fractional_divider_ops from wide audience
  clk: fractional-divider: Export approximation algorithm to the CCF users
      1faa7cb2
    • Stephen Boyd's avatar
      Merge branches 'clk-renesas', 'clk-cleanup' and 'clk-determine-divider' into clk-next · 7110569a
      Stephen Boyd authored 
       - Migrate some clk drivers to clk_divider_ops.determine_rate

* clk-renesas:
  clk: renesas: Make CLK_R9A06G032 invisible
  clk: renesas: r9a07g044: Add entry for fixed clock P0_DIV2
  dt-bindings: clock: r9a07g044-cpg: Add entry for P0_DIV2 core clock
  clk: renesas: r9a07g044: Add clock and reset entries for ADC
  clk: renesas: r9a07g044: Add clock and reset entries for CANFD
  clk: renesas: Rename renesas-rzg2l-cpg.[ch] to rzg2l-cpg.[ch]
  clk: renesas: r9a07g044: Add GPIO clock and reset entries
  clk: renesas: r9a07g044: Add SSIF-2 clock and reset entries
  clk: renesas: r9a07g044: Add USB clocks/resets
  clk: renesas: r9a07g044: Add DMAC clocks/resets
  clk: renesas: r9a07g044: Add I2C clocks/resets
  clk: renesas: r8a779a0: Add the DSI clocks
  clk: renesas: r8a779a0: Add the DU clock
  clk: renesas: rzg2: Rename i2c-dvfs to iic-pmic
  clk: renesas: rzg2l: Fix off-by-one check in rzg2l_cpg_clk_src_twocell_get()
  clk: renesas: rzg2l: Avoid mixing error pointers and NULL
  clk: renesas: rzg2l: Fix a double free on error
  clk: renesas: rzg2l: Fix return value and unused assignment
  clk: renesas: rzg2l: Remove unneeded semicolon

* clk-cleanup:
  clk: palmas: Add a missing SPDX license header
  clk: Align provider-specific CLK_* bit definitions

* clk-determine-divider:
  clk: stm32mp1: Switch to clk_divider.determine_rate
  clk: stm32h7: Switch to clk_divider.determine_rate
  clk: stm32f4: Switch to clk_divider.determine_rate
  clk: bcm2835: Switch to clk_divider.determine_rate
  clk: divider: Implement and wire up .determine_rate by default
      7110569a
    • Stephen Boyd's avatar
      Merge branches 'clk-qcom', 'clk-socfpga', 'clk-mediatek', 'clk-lmk' and 'clk-x86' into clk-next · 4990d8c1
      Stephen Boyd authored 
       - Support video, gpu, display clks on qcom sc7280 SoCs
 - GCC clks on qcom MSM8953, SM4250/6115, and SM6350 SoCs
 - Multimedia clks (MMCC) on qcom MSM8994/MSM8992
 - Migrate to clk_parent_data in gcc-sdm660
 - RPMh clks on qcom SM6350 SoCs
 - Support for Mediatek MT8192 SoCs

* clk-qcom: (38 commits)
  clk: qcom: Add SM6350 GCC driver
  dt-bindings: clock: Add SM6350 GCC clock bindings
  clk: qcom: rpmh: Add support for RPMH clocks on SM6350
  dt-bindings: clock: Add RPMHCC bindings for SM6350
  clk: qcom: adjust selects for SM_VIDEOCC_8150 and SM_VIDEOCC_8250
  clk: qcom: Add Global Clock controller (GCC) driver for SM6115
  dt-bindings: clk: qcom: gcc-sm6115: Document SM6115 GCC
  clk: qcom: mmcc-msm8994: Add MSM8992 support
  clk: qcom: Add msm8994 MMCC driver
  dt-bindings: clock: Add support for MSM8992/4 MMCC
  clk: qcom: Add Global Clock Controller driver for MSM8953
  dt-bindings: clock: add Qualcomm MSM8953 GCC driver bindings
  clk: qcom: gcc-sdm660: Replace usage of parent_names
  clk: qcom: gcc-sdm660: Move parent tables after PLLs
  clk: qcom: use devm_pm_runtime_enable and devm_pm_clk_create
  PM: runtime: add devm_pm_clk_create helper
  PM: runtime: add devm_pm_runtime_enable helper
  clk: qcom: a53-pll: Add MSM8939 a53pll support
  dt-bindings: clock: Update qcom,a53pll bindings for MSM8939 support
  clk: qcom: a53pll/mux: Use unique clock name
  ...

* clk-socfpga:
  clk: socfpga: agilex: add the bypass register for s2f_usr0 clock
  clk: socfpga: agilex: fix up s2f_user0_clk representation
  clk: socfpga: agilex: fix the parents of the psi_ref_clk

* clk-mediatek: (22 commits)
  clk: mediatek: make COMMON_CLK_MT8167* depend on COMMON_CLK_MT8167
  clk: mediatek: Add MT8192 vencsys clock support
  clk: mediatek: Add MT8192 vdecsys clock support
  clk: mediatek: Add MT8192 scp adsp clock support
  clk: mediatek: Add MT8192 msdc clock support
  clk: mediatek: Add MT8192 mmsys clock support
  clk: mediatek: Add MT8192 mfgcfg clock support
  clk: mediatek: Add MT8192 mdpsys clock support
  clk: mediatek: Add MT8192 ipesys clock support
  clk: mediatek: Add MT8192 imp i2c wrapper clock support
  clk: mediatek: Add MT8192 imgsys clock support
  clk: mediatek: Add MT8192 camsys clock support
  clk: mediatek: Add MT8192 audio clock support
  clk: mediatek: Add MT8192 basic clocks support
  clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers
  clk: mediatek: Add configurable enable control to mtk_pll_data
  clk: mediatek: Fix asymmetrical PLL enable and disable control
  clk: mediatek: Get regmap without syscon compatible check
  clk: mediatek: Add dt-bindings of MT8192 clocks
  dt-bindings: ARM: Mediatek: Add audsys document binding for MT8192
  ...

* clk-lmk:
  clk: lmk04832: drop redundant fallthrough statements

* clk-x86:
  clk: x86: Rename clk-lpt to more specific clk-lpss-atom
      4990d8c1
  5. Sep 01, 2021
  7. Aug 30, 2021
  9. Aug 29, 2021
  11. Aug 27, 2021