- Sep 16, 2014
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Anson Huang authored
Add thermal sensor support for i.MX6SL. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Alexander Shiyan authored
This patch adds basic devicetree template for i.MX1 based SoCs. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Philipp Zabel authored
Signed-off-by:
Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Michael Olbrich authored
Signed-off-by:
Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Michael Olbrich authored
Signed-off-by:
Michael Olbrich <m.olbrich@pengutronix.de> Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Lucas Stach authored
Everything in the PCI specification assumes devices to be enumerable on startup. This is only possible if they have power available. A future improvement may allow this regulator to be switched off for D3hot and D3cold power states, but there is a lot of work to do the pcie host controller side for this to work. To keep things simple always enable the regulator for now. Signed-off-by:
Lucas Stach <l.stach@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Stefan Agner authored
The Colibri VF61 is a module which needs a carrier board to actually run. Different carrier board have different hardware support, hence we should reflect this in the device tree files. This patch adds the Colibri Evaluation Board, which supports almost all peripherals defined in the Colibri standard. Also align the compatible naming, file splitting and file naming with the scheme which was choosen for the Tegra based modules. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
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Shawn Guo authored
Immutable branch between MFD and some ARM sub-arch maintainers.
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Fabio Estevam authored
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by default. The fsl sai driver is used by the vf610-twr board, so let's enable it by default. simple-audio-card driver is used by the vf610-twr board, so let's enable it by default. Generated this patch by doing: - make imx_v6_v7_defconfig - make menuconfig and manually select options - make savedefconfig - cp defconfig arch/arm/configs/imx_v6_v7_defconfig ,which results in some additional cleanups. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Fabio Estevam authored
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by default. Generated this patch by doing: - make imx_v4_v5_defconfig - make menuconfig and manually select CONFIG_IMX_WEIM - make savedefconfig - cp defconfig arch/arm/configs/imx_v4_v5_defconfig ,which results in some additional cleanups. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Joe Perches authored
Use the more common pr_warn. Signed-off-by:
Joe Perches <joe@perches.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Anson Huang authored
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Anson Huang authored
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <B38611@freescale.com> for spotting the error. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shengjiu Wang authored
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by:
Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shengjiu Wang authored
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by:
Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shengjiu Wang authored
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by:
Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Fancy Fang authored
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by:
Fancy Fang <chen.fang@freescale.com> Signed-off-by:
Robby Cai <R63905@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shengjiu Wang authored
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by:
Shengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Fabio Estevam authored
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Fabio Estevam authored
Currently csi_lcdif_sels[] is a shared array for the providing the possible clock parents for csi and lcdif blocks. This is not correct, as csi and lcdif do not share the same clock parents. Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in order to describe the parents correctly. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Stefan Agner authored
This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by:
Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Anson Huang authored
Add cpufreq support for i.MX6SX, using common i.MX6Q cpufreq driver. Signed-off-by:
Anson Huang <b20788@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Stefan Agner authored
At the end of the boot process, the clock framework might disable required main PLL's. So far, this was no issue since drivers requested clocks, which are descended of the main PLL's (e.g. pll1_pfd1, which provides the system clock). To archive the full 500MHz system clock, DDR clock need to be a descendant of PLL2 rather than PLL1 (DDRC_CLK_SEL set to 0). The bootloader sets up the clocks accordingly before making use of DDR at all. However, in Linux, there is no driver using PLL2, which lead to PLL2 being disabled by the clock framework. With this patch, we make sure that the main system clock and the DDR clock are initially enabled and are kept enabled. Signed-off-by:
Stefan Agner <stefan@agner.ch> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Alexander Shiyan authored
This patch adds basic devicetree support for i.MX1 based SoCs. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Jason Liu authored
Add more revision support for the new i.MX6DQ tape-out (TO1.5). This TO1.5 is the Rev 1.3 as documented in i.MX6DQ data sheet, because TO1.3 and TO1.4 are never revealed. Signed-off-by:
Jason Liu <r64343@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com> Acked-by:
Sascha Hauer <s.hauer@pengutronix.de>
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- Sep 10, 2014
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Fabio Estevam authored
All the current support of mach-mxt_td60 board can be converted to devicetree. Remove the board file. Cc: Alan Carvalho de Assis <acassis@gmail.com> Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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- Sep 01, 2014
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Alexander Shiyan authored
mx1ads.c can be replaced with devicetree equivalent: imx1-ads.dts, so remove the board file. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Xiubo Li authored
This was added by: Commit 8128c4f3 ("ARM: dts: vf610-twr: Add simple-card support.") This useless property may cause some confusions for users. Signed-off-by:
Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Shawn Guo authored
With commit c716483c ("ARM: 8122/1: smp_scu: enable SCU standby support"), the STANDBY bit of SCU is handled by core function scu_enable(). So imx_scu_standby_enable() can be removed now. Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Alexander Shiyan authored
pcm970-baseboard.c and mach-pcm038.c can be replaced with their devicetree equivalents: imx27-phytec-phycore-rdk.dts and imx27-phytec-phycore-som.dtsi respectively, so remove the board files. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Alexander Shiyan authored
eukrea_mbimx27-baseboard.c and mach-cpuimx27.c can be replaced with their devicetree equivalents: imx27-eukrea-mbimxsd27-baseboard.dts and imx27-eukrea-cpuimx27.dtsi respectively, so remove the board files. Signed-off-by:
Alexander Shiyan <shc_work@mail.ru> Acked-by:
Eric Bénard <eric@eukrea.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Alexander Stein authored
The iomux function declarations are in headers only accessible in this directory. Thus those can't be used in any module. None of the objects in this directory is tristate. Neither can the header be included in out-of-tree modules. Signed-off-by:
Alexander Stein <alexander.stein@systec-electronic.com> Signed-off-by:
Shawn Guo <shawn.guo@freescale.com>
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Linus Torvalds authored
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