Skip to content
  1. Jan 25, 2019
    • Claudiu Manoil's avatar
      enetc: Add ethtool statistics · 16eb4c85
      Claudiu Manoil authored
      
      
      This adds most h/w statistics counters: non-privileged SI conters, as
      well as privileged Port and MAC counters available only to the PF.
      Per ring software stats are also included.
      
      Signed-off-by: default avatarAlex Marginean <alexandru.marginean@nxp.com>
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      16eb4c85
    • Claudiu Manoil's avatar
      enetc: Introduce basic PF and VF ENETC ethernet drivers · d4fd0404
      Claudiu Manoil authored
      
      
      ENETC is a multi-port virtualized Ethernet controller supporting GbE
      designs and Time-Sensitive Networking (TSN) functionality.
      ENETC is operating as an SR-IOV multi-PF capable Root Complex Integrated
      Endpoint (RCIE).  As such, it contains multiple physical (PF) and
      virtual (VF) PCIe functions, discoverable by standard PCI Express.
      
      Introduce basic PF and VF ENETC ethernet drivers.  The PF has access to
      the ENETC Port registers and resources and makes the required privileged
      configurations for the underlying VF devices.  Common functionality is
      controlled through so called System Interface (SI) register blocks, PFs
      and VFs own a SI each.  Though SI register blocks are almost identical,
      there are a few privileged SI level controls that are accessible only to
      PFs, and so the distinction is made between PF SIs (PSI) and VF SIs (VSI).
      As such, the bulk of the code, including datapath processing, basic h/w
      offload support and generic pci related configuration, is shared between
      the 2 drivers and is factored out in common source files (i.e. enetc.c).
      
      Major functionalities included (for both drivers):
      MSI-X support for Rx and Tx processing, assignment of Rx/Tx BD ring pairs
      to MSI-X entries, multi-queue support, Rx S/G (Rx frame fragmentation) and
      jumbo frame (up to 9600B) support, Rx paged allocation and reuse, Tx S/G
      support (NETIF_F_SG), Rx and Tx checksum offload, PF MAC filtering and
      initial control ring support, VLAN extraction/ insertion, PF Rx VLAN
      CTAG filtering, VF mac address config support, VF VLAN isolation support,
      etc.
      
      Signed-off-by: default avatarClaudiu Manoil <claudiu.manoil@nxp.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      d4fd0404
    • Tariq Toukan's avatar
      net/mlx4_core: A write memory barrier is sufficient in EQ ci update · 5e5b9f62
      Tariq Toukan authored
      
      
      Soften the memory barrier call of mb() by a sufficient wmb() in the
      consumer index update of the event queues.
      
      Suggested-by: default avatarEric Dumazet <edumazet@google.com>
      Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
      Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
      5e5b9f62
  2. Jan 24, 2019
  3. Jan 23, 2019