- May 27, 2015
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Andrew Andrianov authored
DNS-327L is a 2-bay NAS with the following specs: - 512MiB RAM - 128MiB NAND Flash - 1 GbE interface (Marvell PHY) - 1 rear USB 3.0 port (via PCIe USB 3.0 controller) - 2 internal SATA ports handled by the Armada 370: uses 2 gpios for power control - two front 2-color leds (amber + white) for both discs, controlled by the SoC - One white LED handled by SoC (USB) - 3 buttons. Power handled by weltrend, USB and RESET (on the bottom) are wired via GPIOs - Unidentified i2c device at address 0x13 (via i2cdetect) - UART0 providing serial console - Weltrend MCU serving for RTC, temperature, fan control, and power button handling interfaced via UART1 (Handled via userspace dns320l-daemon) Signed-off-by: Andrew Andrianov <andrew@ncrmnt.org> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- May 25, 2015
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Rafał Miłecki authored
Starting with commit 8947e396 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Rafał Miłecki authored
Starting with commit 8947e396 ("Documentation: dt: mtd: replace "nor-jedec" binding with "jedec, spi-nor"") we have "jedec,spi-nor" binding indicating support for JEDEC identification. Use it for all flashes that are supposed to support READ ID op according to the datasheets. Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Imre Kaloz authored
This patch adds support for the Linksys WRT1200AC (Caiman) and the Linksys WRT1900AC v2 (Cobra). Both boards have: - 2 Marvell 88W8864 radios - 1 USB 3.0 port - 1 USB 2.0/eSATAp port - 2 Ethernet interfaces connected to a 88E6176 switch (1x WAN + 4x LAN) - 128MB NAND flash - 512MB RAM gregory.clement@free-electrons.com: use serial0:115200n8 in stdout-path and remove the bootargs part in the chosen node Signed-off-by: Imre Kaloz <kaloz@openwrt.org> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- May 11, 2015
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Imre Kaloz authored
This allows us to reference it later. Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
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Sebastian Hesselbarth authored
With reworked device tree files for Compulab CM-A510 SoM and SBC-A510 base board, now add the correspoding board file to Makefile again. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Sebastian Hesselbarth authored
Existing dts file for Compulab CM-A510 was very limited due to missing hardware. Now that we actually found somebody with that board, properly rework it to provide a CoM/SoM include and a board file for Compulab's SBC-A510. Both the CM-A510 SoM and the SBC-A510 can be configured with different options, so we only enable a minimum set of options. The actual board configuration will have to be set by either the bootloader or user. Although functionally not required, repeat even disabled nodes again to increse their visibility in the dtsi/dts files. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Gabriel Dobato <dobatog@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Sebastian Hesselbarth authored
Prior reworking Dove based Compulab CM-A510 device tree, remove it from the compiled device tree files. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Sebastian Hesselbarth authored
This adds a i2c-mux-pinctrl node to dove.dtsi for the internal i2c mux found on Dove SoCs. Up to now, we had no board using any of the two additional i2c busses, so make sure the change does not break any existing boards. Therefore, we rename the i2c-controller node label to "i2c" and enable it by default. Also, the dedicated sub-bus (now "i2c0") is enabled by default. The two optional sub-busses require additional external pin-muxing, so disable them by default. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Apr 22, 2015
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Mathieu Olivari authored
Add the watchdog related entries to the Krait Processor Sub-system (KPSS) timer IPQ8064 devicetree section. Also, add a fixed-clock description of SLEEP_CLK, which will do for now. Signed-off-by: Josh Cartwright <joshc@codeaurora.org> Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
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- Apr 14, 2015
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Tsahee Zidenberg authored
This patch adds device-tree entry for the internal pci bus on Alpine. Alpine's on-chip devices appear as pci devices on this bus. Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Arnd Bergmann authored
This reverts commit e6f219b8. to fix a build error: arch/arm/boot/dts/mt8135-pinfunc.h:18:40: fatal error: dt-bindings/pinctrl/mt65xx.h: No such file or directory Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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- Apr 08, 2015
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Thomas Petazzoni authored
All Marvell EBU SoCs (Kirkwood, Dove, Orion, Armada) have the capability of changing the location of their internal registers (i.e the registers for most hardware blocks inside the SoC). When coming out of reset, the internal registers are mapped at 0xd0000000, but since years and years, the tradition has been to have the internal registers remapped at 0xf1000000 by the bootloader, and Linux has since then assumed that the internal registers for the SoC were located at 0xf1000000 on Kirkwood, Dove, Orion, etc. Linux has never been aware that those registers are remappable (and there is no way to know where they are mapped at runtime, since the register to configure the address of the registers is itself within the internal registers). Then came the Armada 370 and Armada XP, in which some of the very early silicon steppings had an issue, which forced to use 0xd0000000: the SoC was no longer working properly when the internal registers were remapped at 0xf1000000. This issue is only affecting very early silicon steppings and production steppings are not affected: the issue has been fixed in between. Since what we (Free Electrons) used to do the initial submission of the Armada 370 and Armada XP platforms was evaluation boards with those very early steppings, we submitted Device Tree that assumed the internal registers were mapped at 0xd0000000. This is the case for Armada 370 DB, Armada XP DB and Armada XP GP. However, in practice, since Marvell has been shipping the evaluation boards with production steppings of the SoC, they are shipping those boards with bootloaders that remap the registers to 0xf1000000. We have already changed this internal register address to 0xf1000000 for the Armada XP DB in commit 82066bdb and for the Armada XP GP in commit 91ed3220 (both merged in v3.15). We only recently got our hand on an Armada 370 DB with a production stepping of the SoC, which uses a bootloader that remaps internal registers at 0xf1000000. Therefore, this commit aligns the Armada 370 DB to be like the Armada XP DB and Armada XP GP: assume that the internal registers are mapped at 0xf1000000. We would like to stress out the fact that the usage of 0xd0000000 as the internal register base address was a temporary workaround for early steppings deficiencies, and that the real long-term solution is the usage of 0xf1000000. Having 0xd0000000 is an *accident* in the life of the Marvell platform support in the kernel, as is confirmed by the usage of 0xf1000000 in all previous Marvell platforms (Dove, Kirkwood, Orion). There are unfortunately a number of commercial devices that continue to use 0xd0000000 even though they use production steppings of the SoC, simply because the vendors of such devices have never bothered using a more recent bootloader version from Marvell. There is not much we can do about it, and we plan on keeping 0xd0000000 in the Device Tree of such devices. The main reason for remapping the internal registers at 0xf1000000 instead of 0xd0000000 is that it leaves more space in the 0 -> 4 GB part of the physical address space for RAM. With registers at 0xd0000000, all RAM between 0xd0000000 to 0xffffffff is lost because it's covered by the I/O registers. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Jason Cooper <jason@lakedameon.net> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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- Apr 04, 2015
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Nicolas Ferre authored
After 57a38eff (net: phy: micrel: disable broadcast for KSZ8081/KSZ8091) the macb1 interface refuses to work properly because it tries to cling to address 0 which isn't able to communicate in broadcast with the mac anymore. The micrel phy on the board is actually configured to show up at address 1. Adding the phy node and its real address fixes the issue. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: Johan Hovold <johan@kernel.org> Cc: <stable@vger.kernel.org> #3.19 Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Add ARM common idle state device bindings for cpuidle support for APQ 8064. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Add ARM common idle states device bindings for cpuidle support for APQ 8084. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Add ARM common idle states device bindings for cpuidle support for APQ 8974/8074. Support Standalone power collapse (SPC) idle state (power down that does not affect any SoC idle states) for each cpu. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Update the SAW2 DT bindings to add qcom,apq8064-saw2-v1.1-cpu compatible binding string to configure SPM registers and allow the SPM to put the core in deeper idle states when the core is idle. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Each Krait CPU in the QCOM 8084 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Lina Iyer authored
Each Krait CPU in the QCOM 8074/8974 SoC has an SAW power controller to regulate the power to the cpu and aide the core in entering idle states. Reference the SAW instance and associate the instance with the CPU core. Signed-off-by: Lina Iyer <lina.iyer@linaro.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Kenneth Westfield authored
Model the Qualcomm Technologies LPASS hardware for the ipq806x SOC. Signed-off-by: Kenneth Westfield <kwestfie@codeaurora.org> Acked-by: Banajit Goswami <bgoswami@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Ivan T. Ivanov authored
PMA8084 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using AQP8084 based chipset. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Ivan T. Ivanov authored
PM8841 and PM8941 have 2 SPMI devices per physical package. Add their configuration nodes and include them in boards which are using 8x74 based chipset. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Ivan T. Ivanov authored
Add SPMI PMIC Arbiter configuration nodes for APQ8084 and MSM8974. Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Kumar Gala authored
Add the node for the LPASS clock controller found on a few qcom SoCs so that the clock driver can probe. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> [sboyd@codeaurora.org: Added apq8064 and msm8960 nodes] Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Andy Gross authored
This patch adds TCSR support for use by the GSBI to automatically configure ADM CRCI values based on the GSBI port configuration. Signed-off-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Kumar Gala <galak@codeaurora.org> Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Reported-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Apr 03, 2015
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Sebastian Reichel authored
This adds support for the N900's accelerometer to the Nokia N900 DTS file. Signed-off-by: Sebastian Reichel <sre@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Éric Piel <eric.piel@tremplin-utc.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Kaixu Xia authored
The coresight-default-sink configuration option has been removed from the framework. As such remove it from DT and bindings. Signed-off-by: Kaixu Xia <xiakaixu@huawei.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Peter Griffin authored
Now there are generic phy type constants declared in phy.h, migrate over to using them rather than defining our own. This change has been done as one atomic commit to be bisectable. Note: The values of the defines are the same, so there is no ABI breakage with this patch. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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- Apr 02, 2015
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Masahiro Yamada authored
The "MAKEFLAGS += --include-dir=$(srctree)" line in the top Makefile allows us to do this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Marek <mmarek@suse.cz>
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Olof Johansson authored
File uses dash in the filename, not underscore. Reported-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Olof Johansson <olof@lixom.net>
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- Apr 01, 2015
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Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tero Kristo authored
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and moves some of the generic peripherals under it. System control module support is added to the device tree also, and the existing SCM related functionality is moved under it. Signed-off-by: Tero Kristo <t-kristo@ti.com> Reported-by: Tony Lindgren <tony@atomide.com>
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Tero Kristo authored
This patch creates an l4_wkup interconnect for AM43xx, and moves some of the generic peripherals under it. System control module nodes are moved under this new interconnect also, and the SCM clock layout is changed to use the renamed SCM nodea as the clock provider. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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Tero Kristo authored
Pinmux node should be a reference to the base one, not a complete re-write of it. Having the node like this also prevents modifying the node layout in the base am4372.dtsi file, which is needed for control module changes. Signed-off-by: Tero Kristo <t-kristo@ti.com>
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