- Apr 09, 2013
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Gwenhael Goavec-Merou authored
The APF27Dev is a docking board for an APF27 SOM Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The i.MX6 already has a devicetree node for the GPT, but not yet has the clocks. Add them. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The GPT is the GPT timer found on i.MX SoCs. This patch adds the devicetree node for it. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The GPT is the GPT timer found on i.MX SoCs. This patch adds the devicetree node for it. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The GPT is the GPT timer found on i.MX SoCs. Since this is the first user of the AIPS2 this patch also adds it. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sascha Hauer authored
The GPT is the GPT timer found on i.MX SoCs. This adds the missing GPT devicetree nodes. Also fixup the watchdog register map size along the way. it's 0x1000, not 0x4000. This didn't hurt before as the region was not occupied by another device, but now overlaps with the GPT. Signed-off-by:
Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Fabio Estevam authored
Similarly as it was done for mx6q, use a DT lookup in order to make maintainance task for the clock devices easier. Signed-off-by:
Fabio Estevam <fabio.estevam@freescale.com> Tested-by:
Markus Pargmann <mpa@pengutronix.de> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
Add a second pinctrl group of pins for i2c2. Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
Add ecspi2 group of pins for imx51. Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Gwenhael Goavec-Merou authored
The APF51Dev is a docking board for an APF51 SOM Signed-off-by:
Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sean Cross authored
Allow AUD3 to be used as audio output from the audmux block. Signed-off-by:
Sean Cross <xobs@kosagi.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sean Cross authored
Add groups to allow i2c2 and i2c3 to be used on imx6q. Signed-off-by:
Sean Cross <xobs@kosagi.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Sean Cross authored
Add a group of pins to allow ecspi3 to be used on imx6q. Signed-off-by:
Sean Cross <xobs@kosagi.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Shawn Guo authored
Currently, all imx pinctrl drivers maintain a big array of struct imx_pin_reg which hard-codes data like register offset and mux mode setting for each pin function. Every time a new imx SoC support is added, we need to add such a big mount of data. With moving to single kernel build, it's only matter of time to be blamed on memory consuming. With DTC pre-processor support in place, the patch moves all these data into device tree by redefining the PIN_FUNC_ID in imxXX-pinfunc.h and changing the PIN_FUNC_ID parsing code a little bit. The pin id gets re-numbered based on mux register offset, or config register offset if the pin has no mux register, so that kernel can identify the pin id from register offsets provided by device tree. As a bonus point of the change, those arbitrary magic numbers standing for particular PIN_FUNC_ID in device tree sources are now replaced by macros to improve the readability of dts files. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Dong Aisheng <dong.aisheng@linaro.org> Acked-by:
Linus Walleij <linus.walleij@linaro.org>
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Shawn Guo authored
Replace /include/ (dtc) with #include (C pre-processor) for all imx DT files, so that gcc -E handles the entire include tree, and hence any of those files can #include some other file e.g. for constant definitions. This allows future use of #defines and header files in order to define names for various constants, such as pinctrl settings. Use of those features will increase the readability of the device tree files. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Peter Chen authored
Add USB support for imx6q sabresd board Signed-off-by:
Peter Chen <peter.chen@freescale.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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Dirk Behme authored
Add ARM Cortex A9 Performance Monitor Unit (PMU) support. On i.MX6 a combined interrupt on hardware line #126 is used (i.MX6 TRM: Performance Unit interrupt). For more details see Documentation/devicetree/bindings/arm/pmu.txt Signed-off-by:
Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- Apr 06, 2013
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Stephen Warren authored
The recent dtc+cpp support allows header files and C pre-processor defines/macros to be used when compiling device tree files. These headers will typically define various constants that are part of the device tree bindings. The original patch which set up the dtc+cpp include path only considered using those headers from device tree files. However, most are also useful for kernel code which needs to interpret the device tree. In both the DT files and the kernel, I'd like to include the DT-related headers in the same way, for example, <dt-bindings/gpio/tegra-gpio.h>. That will simplify any text which discusses the DT header locations. Creating a <dt-bindings/> for kernel source to use is as simple as placing files into include/dt-bindings/. However, when compiling DT files, the include path should be restricted so that only the dt-bindings path is available; arbitrary kernel headers shouldn't be exposed. For this reason, create a specific include directory for use by dtc+cpp, and symlink dt-bindings from there to the actual location of include/dt-bindings/. For want of a better location, place this "include chroot" into the existing dts/ directory. arch/*/boot/dts/include/dt-bindings -> ../../../../../include/dt-bindings Some headers used by device tree files may not be useful to the kernel; they may be used simply to aid in constructing the DT file (e.g. macros to create a node), but not define any information that the kernel needs to share. These may be placed directly into arch/*/boot/dts/ along with the DT files themselves. Acked-by:
Michal Marek <mmarek@suse.cz> Acked-by:
Shawn Guo <shawn.guo@linaro.org> Acked-by:
Rob Herring <rob.herring@calxeda.com> Signed-off-by:
Stephen Warren <swarren@nvidia.com>
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- Mar 23, 2013
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Laxman Dewangan authored
Fix typo on register address of slink3 controller where register address is wrongly set as 0x7000d480 but it is 0x7000d800. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Mar 13, 2013
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Richard Genoud authored
There was only chip enable and readdy/busy pins for the nand controller. This add the rest of the pins. pinctrl_nand_16bits contains the specific muxes for 16 bits NANDs. Signed-off-by:
Richard Genoud <richard.genoud@gmail.com> Acked-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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Richard Genoud authored
Comments on NAND pins where inverted. Signed-off-by:
Richard Genoud <richard.genoud@gmail.com> Acked-by:
Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by:
Nicolas Ferre <nicolas.ferre@atmel.com>
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- Mar 12, 2013
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Arnd Bergmann authored
The ab8500 device is a child of the prcmu device, which is a memory mapped bus device, whose children are addressable using physical memory addresses, not using mailboxes, so a mailbox number in the ab8500 node cannot be parsed by DT. Nothing uses this number, since it was only introduced as part of the failed attempt to clean up prcmu mailbox handling, and we can simply remove it. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com>
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Padmavathi Venna authored
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on SOCFPGA platform. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Signed-off-by:
Arnd Bergmann <arnd@arndb.de>
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- Mar 09, 2013
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Thomas Petazzoni authored
The orion5x-lacie-ethernet-disk-mini-v2.dts file was using "marvell-orion5x-88f5182" as a compatible string, while it should have been "marvell,orion5x-88f5182". Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
There is no need to have a #address-cells property in the MPIC Device Tree node, and more than that, having it confuses the of_irq_map_raw() logic, which will be used by the Marvell PCIe driver. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Heikki Krogerus authored
Setting the reg-io-width to 1 byte represents more accurate description of the HW. This will fix an issue where UART driver causes kernel panic during bootup. Gregory CLEMENT traced the issue to autoconfig() in 8250.c, where the existence of FIFO is checked from UART_IIR register. The register is now read as 32-bit value as the reg-io-width is set to 4-bytes. The retuned value seems to contain bogus data for bits 31:8, causing the issue. Signed-off-by:
Heikki Krogerus <heikki.krogerus@linux.intel.com> Cc: Gregory CLEMENT <gregory.clement@free-electrons.com> Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by:
Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com> Tested-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Jean-Francois Moine authored
The commit: 48be9ac9 ARM: Dove: split legacy and DT setup removed the RTC initialization. This patch re-enables the RTC via the DT. Signed-off-by:
Jean-François Moine <moinejf@free.fr> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Florian Fainelli authored
This patch modifies the Armada 370 Reference Design DTS file to enable support for the two USB ports found on this board. Signed-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Andrew Lunn authored
The Marvell RTC on Kirkwood makes use of the runit clock. Ensure the driver clk_prepare_enable() this clock, otherwise there is a danger the SoC will lockup when accessing RTC registers with the clock disabled. Reported-by:
Simon Baatz <gmbnomis@gmail.com> Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Simon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Andrew Lunn authored
The kirkwood SoC GPIO cores use the runit clock. Add code to clk_prepare_enable() runit, otherwise there is a danger of locking up the SoC by accessing the GPIO registers when runit clock is not ticking. Reported-by:
Simon Baatz <gmbnomis@gmail.com> Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Tested-by:
Simon Baatz <gmbnomis@gmail.com> Acked-by:
Linus Walleij <linus.walleij@linaro.org> Cc: <stable@vger.kernel.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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Jason Cooper authored
When DT support for kirkwood was first introduced, there was no clock infrastructure. As a result, we had to manually pass the clock-frequency to the driver from the device node. Unfortunately, on kirkwood, with minimal config or all module configs, clock-frequency breaks booting because of_serial doesn't consume the gate_clk when clock-frequency is defined. The end result on kirkwood is that runit gets gated, and then the boot fails when the kernel tries to write to the serial port. Fix the issue by removing the clock-frequency parameter from all kirkwood dts files. Booted on dreamplug without earlyprintk and successfully logged in via ttyS0. Reported-by:
Simon Baatz <gmbnomis@gmail.com> Tested-by:
Simon Baatz <gmbnomis@gmail.com> Cc: <stable@vger.kernel.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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- Mar 07, 2013
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Padmavathi Venna authored
This patch adds #dma-cells property to PL330 DMA controller nodes for supporting generic dma dt bindings on samsung exynos platforms. #dma-channels and #dma-requests are not required now but added in advance. Signed-off-by:
Padmavathi Venna <padma.v@samsung.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Kukjin Kim <kgene.kim@samsung.com>
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Jonathan Austin authored
Before jumping to (position independent) C-code from the decompressor's assembler world we set-up the C environment. This setup currently does not set r9, which for arm-none-uclinux-uclibceabi toolchains is by default expected to be the PIC offset base register (IE should point to the beginning of the GOT). Currently, therefore, in order to build working kernels that use the decompressor it is necessary to use an arm-linux-gnueabi toolchain, or similar. uClinux toolchains cause a prefetch abort to occur at the beginning of the decompress_kernel function. This patch allows uClinux toolchains to build bootable zImages by forcing the -mno-single-pic-base option, which ensures that the location of the GOT is re-derived each time it is required, and r9 becomes free for use as a general purpose register. This has a small (4% in instruction terms) advantage over the alternative of setting r9 to point to the GOT before calling into the C-world. Signed-off-by:
Jonathan Austin <jonathan.austin@arm.com> Acked-by:
Nicolas Pitre <nico@linaro.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- Mar 05, 2013
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Prashant Gaikwad authored
As DT support for clocks and smp_twd is enabled, add clock entry for smp_twd clock to DT. This fixes the following error while booting the kernel: smp_twd: clock not found -2 Signed-off-by:
Prashant Gaikwad <pgaikwad@nvidia.com> [swarren: include kernel log spew that this fixes] Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Nishanth Menon authored
commit 5f300acd (ARM: 7152/1: distclean: Remove generated .dtb files) ensured that dtbs were cleaned up when they were in arch/arm/boot. However, with the following commit: commit 499cd829 (ARM: dt: change .dtb build rules to build in dts directory) make clean now leaves dtbs in arch/arm/boot/dts/ untouched. Include dts directory so that clean-files rule from arch/arm/boot/dts/Makefile is invoked when make clean is done. Cc: Dirk Behme <dirk.behme@de.bosch.com> CC: Grant Likely <grant.likely@secretlab.ca> Signed-off-by:
Nishanth Menon <nm@ti.com> Signed-off-by:
Olof Johansson <olof@lixom.net>
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Stephen Warren authored
BCM2835-ARM-Peripherals.pdf states that the I2C module's input clock is nominally 150MHz, and that value is currently reflected in bcm2835.dtsi. However, practical measurements show that the rate is actually 250MHz, and this agrees with various downstream kernels. Switch the I2C clock's frequency to 250MHz so that the generated bus clock rate is accurate. Signed-off-by:
Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Olof Johansson <olof@lixom.net>
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- Mar 04, 2013
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Shawn Guo authored
According to fsl,imx53-pinctrl.txt, the pin number of DISP1_DAT_21 should be 545, while 543 is IPU_CSI0_D_3. Along with the change, one duplication of DISP1_DAT_0 in disp1-grp1 is removed. Signed-off-by:
Shawn Guo <shawn.guo@linaro.org>
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- Mar 01, 2013
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Florian Fainelli authored
The Armada 370 Reference Design board has one SD card slot, directly connected to the SDIO IP of the SoC, so we enable this IP. there are no GPIOs for card-detect and write-protect so we do not specify any. Signed-off-by:
Florian Fainelli <florian@openwrt.org> Signed-off-by:
Jason Cooper <jason@lakedaemon.net>
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