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Commit ea141d58 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding
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clk: tegra20: Correct PLL_C_OUT1 setup 



PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's
set it to 240 MHz and explicitly specify HCLK rate for consistency.

Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 2dcabf05
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