clk: qoriq: modify MAX_PLL_DIV to 32

On LS2088A, Watchdog need clk divided by 32,
so modify MAX_PLL_DIV to 32

Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>
Link: https://lore.kernel.org/r/20200916030311.17280-1-qiang.zhao@nxp.com


Signed-off-by: Stephen Boyd <sboyd@kernel.org>