fpga: dfl: afu: add header sub feature support
The port header register set is always present for port, it is mainly for capability, control and status of the ports that AFU connected to. This patch implements header sub feature support. Below user interfaces are created by this patch. Sysfs interface: * /sys/class/fpga_region/<regionX>/<dfl-port.x>/id Read-only. Port ID. Ioctl interface: * DFL_FPGA_PORT_RESET Reset the FPGA Port and its AFU. Signed-off-by:Tim Whisonant <tim.whisonant@intel.com> Signed-off-by:
Enno Luebbers <enno.luebbers@intel.com> Signed-off-by:
Shiva Rao <shiva.rao@intel.com> Signed-off-by:
Christopher Rauer <christopher.rauer@intel.com> Signed-off-by:
Xiao Guangrong <guangrong.xiao@linux.intel.com> Signed-off-by:
Wu Hao <hao.wu@intel.com> Acked-by:
Alan Tull <atull@kernel.org> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
parent
47c1b19c
Please register or sign in to comment