Skip to content
Commit dc6fcba7 authored by Guo Ren's avatar Guo Ren Committed by Paul Walmsley
Browse files

riscv: Fixup obvious bug for fp-regs reset



CSR_MISA is defined in Privileged Architectures' spec: 3.1.1 Machine
ISA Register misa. Every bit:1 indicate a feature, so we should beqz
reset_done when there is no F/D bit in csr_misa register.

Signed-off-by: default avatarGuo Ren <ren_guo@c-sky.com>
[paul.walmsley@sifive.com: fix typo in commit message]
Fixes: 9e806356 ("riscv: clear the instruction cache and all registers when booting")
Signed-off-by: default avatarPaul Walmsley <paul.walmsley@sifive.com>
parent 13cf4cf0
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment