ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151
[ Upstream commit db7be2cb ] Referring to the note under USBH reset and clocks chapter of RM0436, "In order to access USBH_OHCI registers it is necessary to activate the USB clocks by enabling the PLL controlled by USBPHYC" (ck_usbo_48m). The point is, when USBPHYC PLL is not enabled, OHCI register access freezes the resume from STANDBY. It is the case when dual USBH is enabled, instead of OTG + single USBH. When OTG is probed, as ck_usbo_48m is USBO clock parent, then USBPHYC PLL is enabled and OHCI register access is OK. This patch adds ck_usbo_48m (provided by USBPHYC PLL) as clock of USBH OHCI, thus USBPHYC PLL will be enabled and OHCI register access will be OK. Signed-off-by:Amelie Delaunay <amelie.delaunay@foss.st.com> Signed-off-by:
Alexandre Torgue <alexandre.torgue@foss.st.com> Signed-off-by:
Sasha Levin <sashal@kernel.org>
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ddec6cbb
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