clk: imx8mm: remove SYS PLL 1/2 clock gates

Remove the PLL 1/2 gates as it make AMP clock management harder without
obvious benifit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Link: https://lore.kernel.org/r/20220225081733.2294166-2-peng.fan@oss.nxp.com


Signed-off-by: Abel Vesa <abel.vesa@nxp.com>