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Commit cb2e7013 authored by Chaitanya Kumar Borah's avatar Chaitanya Kumar Borah Committed by Joonas Lahtinen
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drm/i915/display: Set correct voltage level for 480MHz CDCLK



According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.

BSpec: 49208

Fixes: 06f1b06d ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")

v2: rebase

Signed-off-by: default avatarChaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230529060747.3972259-1-chaitanya.kumar.borah@intel.com


(cherry picked from commit 5a3c46b8)
Signed-off-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
parent 40023959
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