ASoC: rt5677: Set ADC clock to use PLL and enable ASRC

Use the PLL to kept the correct 24M clock rate so frequency shift does
not occur when using the DSP VAD.

Signed-off-by: Curtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org


Signed-off-by: Mark Brown <broonie@kernel.org>