drm/vc4: crtc: Reduce PV fifo threshold on hvs4

Experimentally have found PV on hvs4 reports fifo full
error with expected settings and does not with one less

This appears as:
[drm:drm_atomic_helper_wait_for_flip_done] *ERROR* [CRTC:82:crtc-3] flip_done timed out

with bit 10 of PV_STAT set "HVS driving pixels when the PV FIFO is full"

Signed-off-by: Dom Cobley <popcornmix@gmail.com>