Skip to content
Commit a6b4229d authored by Imre Deak's avatar Imre Deak Committed by Tvrtko Ursulin
Browse files

drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality



A recent bspec update added a restriction on when DC states can be enabled:

[Before enabling DC states:]

"""
PG2 can be kept enabled only because PGB requires PG2.
Do not use PG2 functions, such as type-C DDIs.

DMC will dynamically control PG1, PGA, PG2, PGB.
"""

Accordingly prevent DC states if PW2 (aka PG2) is enabled for any other
functionality.

Bpsec: 49193

Fixes: 88c48793 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2")
Reported-by: default avatarKai Vehmanen <kai.vehmanen@intel.com>
Tested-by: default avatarAmbica Pramod <ambica.pramod@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606172822.1891897-1-imre.deak@intel.com


(cherry picked from commit f4e498eb)
Signed-off-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
parent 274d4b96
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment