xhci: add a quirk to work around a suspected cache bug on VLI controllers

Certain transfer ring access patterns can cause the controller to hang
fetching TRBs for a USB2.0 endpoint.

- If two USB2.0 endpoints are active at once and
- Both endpoints are traversing a Link TRB where the following segment
  has a lower page address and
- One of the endpoints is a Bulk IN and
- The other endpoint is an Interrupt IN

Then the Interrupt IN endpoint can end up not getting polled.
It is unclear what the precise failure mode is, as the controller seems to
haphazardly and repeatedly fetch TRBs for both endpoints but does not
advance the Interrupt endpoint transfer.

As a workaround, add a quirk that initially constrains all USB2.0 transfer
rings to a single segment in size. If for any reason a device driver queues
up enough outstanding transfers to fill the ring segment, then the ring
will be expanded. This has not been seen to occur with UMS or UVC drivers,
which aggressively queue buffers.

Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>