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Commit 96f3b978 authored by Dmitry Rokosov's avatar Dmitry Rokosov Committed by Jerome Brunet
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dt-bindings: clock: meson: a1: pll: introduce new syspll bindings



The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.

The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.

Signed-off-by: default avatarDmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: default avatarRob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com


Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
parent fc1c7f94
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