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Unverified Commit 956d705d authored by Damien Le Moal's avatar Damien Le Moal Committed by Palmer Dabbelt
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riscv: Unaligned load/store handling for M_MODE



Add handlers for unaligned load and store traps that may be generated
by applications. Code heavily inspired from the OpenSBI project.
Handling of the unaligned access traps is suitable for applications
compiled with or without compressed instructions and is independent of
the kernel CONFIG_RISCV_ISA_C option value.

Signed-off-by: default avatarDamien Le Moal <damien.lemoal@wdc.com>
Signed-off-by: default avatarAnup Patel <anup.patel@wdc.com>
Signed-off-by: default avatarPalmer Dabbelt <palmerdabbelt@google.com>
parent f1e58583
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