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Commit 8f076761 authored by Andrea Venturi's avatar Andrea Venturi Committed by Maxime Ripard
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clk: sunxi: mod1 clock should modify it's parent 



add CLK_SET_RATE_PARENT to modify the rate on clk upstream

Signed-off-by: default avatarMarcus Cooper <codekipper@gmail.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 92a39d90
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