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Commit 7660f633 authored by Dong Aisheng's avatar Dong Aisheng Committed by Marc Kleine-Budde
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can: m_can: add missing delay after setting CCCR_INIT bit



The spec mentions there may be a delay until the value written to INIT can be
read back due to the synchronization mechanism between the two clock domains.
But it does not indicate the exact clock cycles needed. The 5us delay is a
test value and seems ok.

Without the delay, CCCR.CCE bit may fail to be set and then the initialization
fail sometimes when do repeatly up and down.

Signed-off-by: default avatarDong Aisheng <b29396@freescale.com>
Signed-off-by: default avatarMarc Kleine-Budde <mkl@pengutronix.de>
parent 921f1681
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