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Commit 75fe45a0 authored by Wolfram Sang's avatar Wolfram Sang Committed by Geert Uytterhoeven
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clk: renesas: r8a779f0: Add SDHI0 clock 



Signed-off-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20220603233437.21819-1-wsa+renesas@sang-engineering.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 61a6737f
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