Skip to content
Commit 758e8366 authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Jason Cooper
Browse files

irqchip: armada-370-xp: Fix MPIC interrupt handling



In both Armada-375 and Armada-38x MPIC interrupts should be identified by
reading cause register multiplied by the interrupt mask.

A lack of above mentioned multiplication resulted in a bug, caused by the
fact that in Armada-375 and Armada-38x some of the interrupts
(e.g. network interrupts) can be handled either as a GIC or MPIC interrupts.
Therefore during MPIC interrupts handling, cause register shows hits from
interrupts even if they are masked for MPIC but unmasked for a GIC.

This resulted in 'bad IRQ' error, because masked MPIC interrupt without
registered interrupt handler, was trying to be handled during interrupt
handling procedure of some other unmasked MPIC interrupt (e.g. local timer
irq).

This commit fixes that by ensuring that during MPIC interrupt handling only
interrupts that are unmasked for MPIC are processed.

Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Fixes: bc69b8ad ("irqchip: armada-370-xp: Setup a chained handler for the MPIC")
Cc: <stable@vger.kernel.org> # v3.15+
Acked-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Link: https://lkml.kernel.org/r/1411643839-64925-3-git-send-email-jaz@semihalf.com


Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 298dcb2d
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment