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Commit 74c344e6 authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Russell King (Oracle)
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ARM: 9267/1: Define Armv8 registers in AArch32 state



AArch32 Instruction Set Attribute Register 6 (ID_ISAR6_EL1) and AArch32
Processor Feature Register 2 (ID_PFR2_EL1) identifies some new features
for the Armv8 architecture. This registers will be utilized to add
hwcaps for those cpu features.

These registers are marked as reserved for Armv7 and should be a RAZ.

Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
Signed-off-by: default avatarRussell King (Oracle) <rmk+kernel@armlinux.org.uk>
parent f424f2c1
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