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Commit 6ff9cb53 authored by Biju Das's avatar Biju Das Committed by Geert Uytterhoeven
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clk: renesas: Add r8a7744 CPG Core Clock Definitions



Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's
Manual.

Signed-off-by: default avatarBiju Das <biju.das@bp.renesas.com>
Reviewed-by: default avatarFabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent bbd71915
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