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Unverified Commit 6f002c57 authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Maxime Ripard
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ARM: dts: sun8i: s3: add devicetree for Lichee zero plus w/ S3



Lichee zero plus is a core board made by Sipeed, which includes on-board
TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
header, a microUSB slot and a gold finger connector for expansion. It
can use either Sochip S3 or Allwinner S3L SoC.

Add the basic device tree for the core board, w/o optional onboard
storage, and with S3 SoC.

Signed-off-by: default avatarIcenowy Zheng <icenowy@aosc.io>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
parent 11d1bdea
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