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Commit 6e8b1dcb authored by Cong Dang's avatar Cong Dang Committed by Geert Uytterhoeven
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clk: renesas: r8a779h0: Add watchdog clock



Add the module clock used by the RCLK Watchdog Timer on the Renesas
R-Car V4M (R8A779H0) SoC.

Signed-off-by: default avatarCong Dang <cong.dang.xn@renesas.com>
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/f1dbf0f3f484015f2e629d78b746cf377d6f6746.1706790015.git.geert+renesas@glider.be
parent 62527c9d
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