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Commit 6a7bafe8 authored by Vandita Kulkarni's avatar Vandita Kulkarni Committed by José Roberto de Souza
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drm/i915/ehl/dsi: Set lane latency optimization for DW1



EHL has 2 additional steps in the DSI sequence, this is one of then
the lane latency optimization for DW1.

BSpec: 20597
Cc: Uma Shankar <uma.shankar@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarVandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: default avatarJosé Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190619233134.20009-1-jose.souza@intel.com
parent 60a0933b
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