drm/panel-simple: Increase pixel clock on Pi 7inch panel

The Toshiba bridge is very fussy and doesn't like the CM3
output when being told to produce a 27.777MHz pixel clock, which
is an almost perfect match to the DSI link integer divider.

Increasing to 30MHz will switch the DSI link from 333MHz to 400MHz
and makes the bridge happy with the same video timing as works
on Pi4.
(Pi4 will be using a link frequency of 375MHz due to a 3GHz
parent PLL).

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>