spi: dw-dma: Get the last DMA scoop out of the FIFO

With a DMA FIFO threshold greater than 1 (encoded as 0), it is possible
for data in the FIFO to be inaccessible, causing the transfer to fail
after a timeout. If the transfer includes a transmission, reduce the
RX threshold when the TX completes, otherwise use 1 for the whole
transfer (inefficient, but not catastrophic at SPI data rates).

See: https://github.com/raspberrypi/linux/issues/5696



Signed-off-by: Phil Elwell <phil@raspberrypi.com>