PCI: tegra194: Fix Root Port interrupt handling
As part of Root Port interrupt handling, level-0 register is read first and based on the bits set in that, corresponding level-1 registers are read for further interrupt processing. Since both these values are currently read into the same 'val' variable, checking level-0 bits the second time around is happening on the 'val' variable value of level-1 register contents instead of freshly reading the level-0 value again. Fix by using different variables to store level-0 and level-1 registers contents. Link: https://lore.kernel.org/r/20220721142052.25971-11-vidyas@nvidia.com Fixes: 56e15a23 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by:Vidya Sagar <vidyas@nvidia.com> Signed-off-by:
Bjorn Helgaas <bhelgaas@google.com>
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