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Commit 64ded09d authored by Thor Thayer's avatar Thor Thayer Committed by Dinh Nguyen
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ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry 



Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.

Signed-off-by: default avatarThor Thayer <tthayer@opensource.altera.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@opensource.altera.com>
parent 95c16caa
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