Skip to content
Commit 63f40a7f authored by Yongqiang Niu's avatar Yongqiang Niu Committed by Jassi Brar
Browse files

mailbox: mtk-cmdq: add gce software ddr enable private data



if gce work control by software, we need set software enable
for MT8186 Soc

there is a handshake flow between gce and ddr hardware,
if not set ddr enable flag of gce, ddr will fall into idle
mode, then gce instructions will not process done.
we need set this flag of gce to tell ddr when gce is idle or busy
controlled by software flow.

0x48[2:0] means control by software
0x48[18:16] means ddr enable
0x48[2:0] is pre-condition of 0x48[18:16].
if we want set 0x48[18:16] ddr enable, 0x48[2:0] must be set at same
time.
and only these bits is useful, other bits is useless bits

Signed-off-by: default avatarYongqiang Niu <yongqiang.niu@mediatek.com>
Reviewed-by: default avatarCK Hu <ck.hu@mediatek.com>
Signed-off-by: default avatarJassi Brar <jaswinder.singh@linaro.org>
parent 23ba2e7f
Loading
Loading
Loading
Loading
0% Loading or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment