riscv: Fixed wrong register in XIP_FIXUP_FLASH_OFFSET macro

During the refactoring, a bug was introduced in the rarly used
XIP_FIXUP_FLASH_OFFSET macro.

Fixes: bee7fbc3 ("RISC-V CPU Idle Support")
Fixes: e7681beb ("RISC-V: Split out the XIP fixups into their own file")

Signed-off-by: Frederik Haxel <haxel@fzi.de>
Link: https://lore.kernel.org/r/20231212130116.848530-3-haxel@fzi.de


Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>