drm/vc4: dsi: Correct max divider to 255 (not 7)

The integer divider from parent PLL to DSI clock is capable
of going up to /255, not just /7 that the driver was trying.
This allows for slower link frequencies on the DSI bus where
the resolution permits.

Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>