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Commit 5cee04a8 authored by Neil Armstrong's avatar Neil Armstrong Committed by Vinod Koul
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phy: qcom: qmp-pcie: register PHY AUX clock for SM8[456]50 4x2 PCIe PHY



The PCIe Gen4x2 PHY found in the SM8[456]50 SoCs have a second clock,
enable this second clock by setting the proper 20MHz hardware rate in
the Gen4x2 SM8[456]50 aux_clock_rate config fields.

Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: default avatarNeil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240322-topic-sm8x50-upstream-pcie-1-phy-aux-clk-v2-4-3ec0a966d52f@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 583ca9cc
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