clk: renesas: r9a07g043: Add SDHI clock and reset entries

Add SDHI{0,1} mux, clock and reset entries to CPG driver

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220402074626.25624-5-biju.das.jz@bp.renesas.com


Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>